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| PRELIMINARY FEBRUARY 2004 XRT83L34 REV. P1.3.4 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR GENERAL DESCRIPTION The XRT83L34 is a fully integrated Quad (four channel) long-haul and short-haul line interface unit for T1 (1.544Mbps) 100, E1 (2.048Mbps) 75 or 120, or J1 110 applications. In long-haul applications the XRT83L34 accepts signals that have been attenuated from 0 to 36dB at 772kHz in T1 mode (equivalent of 0 to 6000 feet of cable loss) or 0 to 43dB at 1024kHz in E1 mode. In T1 applications, the XRT83L34 can generate five transmit pulse shapes to meet the short-haul Digital Cross-Connect (DSX-1) template requirements as well as for Channel Service Units (CSU) Line Build Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB as required by FCC rules. It also provides programmable transmit pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions. The XRT83L34 provides both a parallel Host microprocessor interface as well as a Hardware mode for programming and control. Both the B8ZS and HDB3 encoding and decoding functions are selectable as well as AMI. An on-chip crystal-less jitter attenuator with a 32 or 64 bit FIFO can be placed either in the receive or the transmit path with loop bandwidths of less than 3Hz. The XRT83L34 provides a variety of loop-back and diagnostic features as well as transmit driver short circuit detection and receive loss of signal monitoring. It supports internal impedance matching for 75, 100, 110 and 120 for both transmitter and receiver. In the absence of the power supply, the transmit outputs and receive inputs are tri-stated allowing for redundancy applications The chip includes an integrated programmable clock multiplier that can synthesize T1 or E1 master clocks from a variety of external clock sources. APPLICATIONS * T1 Digital Cross-Connects (DSX-1) * ISDN Primary Rate Interface * CSU/DSU E1/T1/J1 Interface * T1/E1/J1 LAN/WAN Routers * Public switching Systems and PBX Interfaces * T1/E1/J1 Multiplexer and Channel Banks Features (See Page 2) FIGURE 1 BLOCK DIAGRAM OF THE XRT83L34 T1/E1/J1 LIU (HOST MODE) MCLK E1 MCLK T1 MASTER CLO CK SYNTH ESIZER MCLKO UT O ne of four channels, CHANNEL_n - (n= 0:3) TPO S_n/TDATA _n TNE G_n/CO DES _n TCLK _n TAO S ENABLE TX FILTER & PULSE SHAPER DFM D RIVE MON ITO R DMO _n TTIP_n TRING _n Q RSS PATTER N GEN ERATO R HDB 3/ B8ZS ENCO DER TX/R X JIT TER ATT ENUATO R TIMIN G CO NTR O L LINE DRIVER LBO [3:0] JA SELECT Q RSS ENABLE REM OT E LO OPB AC K D IG ITAL LO OPB AC K LO O PBACK ENABLE T IMING & DATA REC O VERY PEAK DET ECTO R & S LICER LO CAL ANALOG LO O PBACK TXON_n Q RSS D ETECT OR RCLK _n RNE G_n/LCV _n RP OS_n/RDATA _n NETW OR K LOO P D ETECT OR HDB 3/ B8ZS DECO DER TX/R X JIT TER ATT ENUATO R RX EQ UALIZER RTIP_n RRING_n NLCD EN AB LE LO S DETEC TO R AIS DETEC TO R EQ UALIZER C ON TRO L RLOS _n HW /HO ST W R_R/W RD_DS ALE_AS CS RDY_DTACK INT TEST MIC RO PRO CESSO R CO NT RO LLER ICT P TS1 P TS2 D[7:0] P CLK A[7:0] RE SET Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 FIGURE 2 BLOCK DIAGRAM OF THE XRT83L34 T1/E1/J1 LIU (HARDWARE MODE) MCLKE1 MCLKT1 CLKSE L[2:0] MASTER CLOC K SYNTH ESIZER MCLKO UT T AO S_n One of four Channels, CHANNEL_n - (n=0 : 3) TPOS_n/TDA TA_n TNEG _n/CODES_n TCLK_n DFM DR IVE MO NITO R DMO_n T T IP_n T RING _n Q RSS PATT ERN GENE RAT OR HDB3/ B8ZS EN CO DER TX/RX JITT ER ATTEN UATOR TIMING CO NTR OL TX FILTER & PULSE SHAPER LINE D RIVER LBO [3:0] JA SELEC T QR SS ENAB LE R EMOT E LO O PBACK D IGITAL LO O PBAC K LOO PBACK ENAB LE TIMIN G & DATA REC OVER Y PEAK DETECTO R & SLICER LO CAL AN ALOG LOO PBACK T XO N_n QR SS DET ECTO R RCLK_n RNEG _n/LCV_n RPO S_n/RDA TA_n NETW O RK LO OP DET ECTO R HDB3/ B8ZS D ECO DER TX/RX JITT ER ATTEN UATOR RX EQ UALIZER RTIP_n RRING_n LO OP1_n LO OP0_n NLCD ENABLE LO S DETEC TOR AIS DET ECTO R EQ UALIZER CO NTR OL RLO S_n HW /HO ST G AUG E JASEL1 JASEL0 RXT SEL T XT SEL T ERSEL1 T ERSEL0 RXRES1 RXRES0 TEST ICT RESET T RAT IO SR/DR EQ C[4:0] T CLKE RCLKE RXMUT E AT AO S HARW AR E C ON TRO L FEATURES * Internal and/or external impedance matching for 75, 100, 110 and 120 * Fully integrated four channel long-haul or shorthaul transceivers for E1,T1 or J1 applications * Tri-State transmit output and receive input capability for redundancy applications * Adaptive Receive Equalizer for up to 36dB cable attenuation * Provides High Impedance for Tx and Rx during power off * Programable Transmit Pulse Shaper for E1,T1 or J1 short-haul interfaces * Transmit return loss meets or exceeds ETSI 300166 standard * Five fixed transmit pulse settings for T1 short-haul applications plus a fully programmable waveform generator for transmit output pulse shaping that can be used for both T1 and E1 modes. * On-chip digital clock recovery circuit for high input jitter tolerance * Transmit Line Build-Outs (LBO) for T1 long-haul application from 0dB to -22.5dB in three 7.5dB steps * Crystal-less digital jitter attenuator with 32-bit or 64bit FIFO selectable either in transmit or receive path * On-chip frequency multiplier generates T1 or E1 Master clocks from variety of external clock sources * Selectable receiver sensitivity from 0 to 36dB cable loss for T1 @772kHz and 0 to 43dB for E1 @1024kHz * High receiver interference immunity * On-chip transmit short-circuit protection and limiting, and driver fail monitor output (DMO) * Receive monitor mode handles 0 to 29dB resistive attenuation along with 0 to 6dB of cable attenuation for E1 and 0 to 3dB of cable attenuation for T1 modes * Receive loss of signal (RLOS) output * On-chip HDB3/B8ZS/AMI encoder/decoder functions * Supports 75 and 120 (E1), 100 (T1) and 110 (J1) applications * QRSS pattern generator and detection for testing and monitoring * Error and Bipolar Violation Insertion and Detection 2 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY * Receiver Line Attenuation Indication Output in 1dB steps T1.403 and T1.408; ETSI 300-166 and AT&T Pub 62411 * Network Loop-Code Detection for automatic LoopBack Activation/Deactivation * Supports both Hardware and Host (parallel Microprocessor) interface for programming * Transmit All Ones (TAOS) and In-Band Network Loop Up and Down code generators * Supports Local Analog, Remote, Digital and Dual Loop-Back Modes * Meets or exceeds T1 and E1 short-haul and longhaul network access specifications in ITU G.703, G.775, G.736 and G.823; TR-TSY-000499; ANSI * Programmable Interrupt * Low power dissipation * Logic inputs accept either 3.3V or 5V levels * Single 3.3V Supply Operation * 128 pin TQFP package * -40C to +85C Temperature Range ORDERING INFORMATION PART NUMBER XRT83L34IV PACKAGE 128 Lead TQFP (14 x 20 x 1.4mm) OPERATING TEMPERATURE RANGE -40C to +85C 3 PRELIMINARY FIGURE 3 PIN OUT OF THE XRT83L34 TCLK _2 TP O S _2/TD A TA _2 TN E G _2/C O D E S _2 u P T S 1/RC LK E uP TS 2/TC LK E RXRES0 RXRES1 RX TS E L TX TS E L TE R S E L1 TE R S E L0 GND DVDD DVDD DGND DGND IN T/TRA TIO ICT RE S E T TX O N _0 TX O N _1 TX O N _2 TX O N _3 TN E G _1/C O D E S _1 TP O S _1/TD A TA _1 TCLK _1 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 XRT83L34 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR 4 T C LK _0 TP O S _0/TD A T A _0 TN E G _0/C O D E S _0 R LO S _0 R C LK _ 0 R N E G _0/LCV _0 R P O S _0/R D A TA _0 RV DD _0 R TIP _0 R R ING _0 R G ND _ 0 TG N D _0 T T IP _0 TV DD _0 TR ING _0 S R /DR TR ING _1 TV D D _1 T T IP _1 TG ND _1 R G ND _1 R R ING _1 R TIP _1 RV D D _1 R P O S _1/R D A TA _1 R N E G _1/LC V _1 R C LK _1 R LO S _1 DV DD V D D P LL_1 V D DP LL_2 M CLK E 1 M CLK T1 G N D P LL_1 G N D P L L_2 M C LK O U T C L K S E L0 C LK S E L1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 TCLK_3 TPOS_3/TDATA_3 TNEG_3/CODES_3 RLOS_3 RCLK_3 RNEG_3/LCV_3 R POS_3/RDATA_3 RVDD_3 RTIP_3 RRING_3 RGND _3 TGN D_3 TTIP_3 TVDD_3 TRING_3 GAUGE TRING_2 TVDD_2 TTIP_2 TGND_2 RGND_2 RRING_2 RTIP_2 RVD D_2 R POS_2/RDATA_2 RNEG_2/LCV_2 RCLK_2 RLOS_2 DGND RDY_DTACK/RXM U TE C S/TAOS_3 ALE_AS/TAOS_2 RD_DS/TAO S_1 W R_R/W /TAOS_0 HW _HO ST DM O_3 DM O_2 DM O_1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 DM O _0 A [0]/E Q C0 A [1]/E Q C1 A [2]/E Q C2 A [3]/E Q C3 A [4]/E Q C4 A [5]/JA S E L0 A [6]/JA S E L1 DG N D DG N D DG N D DV DD DV DD DV DD uP C LK /A TA O S D[0]/LO O P 0_3 D[1]/LO O P 1_3 D[2]/LO O P 0_2 D[3]/LO O P 1_2 D[4]/LO O P 0_1 D[5]/LO O P 1_1 D[6]/LO O P 0_0 D[7]/LO O P 1_0 A G ND AVDD CLK S E L2 REV. P1.3.4 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE OF CONTENTS GENERAL DESCRIPTION ................................................................................................. 1 APPLICATIONS .............................................................................................................................................. Figure 1 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Host Mode) ............................................ Figure 2 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Hardware Mode) ................................... FEATURES .................................................................................................................................................... ORDERING INFORMATION ...................................................................................................................... Figure 3 Pin Out of the XRT83L34 .................................................................................................... 1 1 2 2 3 4 TABLE OF CONTENTS ....................................................................................................... I PIN DESCRIPTION BY FUNCTION ................................................................................... 5 RECEIVE SECTIONS ...................................................................................................................................... 5 TRANSMITTER SECTIONS .............................................................................................................................. 7 MICROPROCESSOR INTERFACE ...................................................................................................................... 9 JITTER ATTENUATOR .................................................................................................................................. 12 CLOCK SYNTHESIZER .................................................................................................................................. 13 ALARM FUNCTION//REDUNDANCY SUPPORT ................................................................................................. 14 POWER AND GROUND ................................................................................................................................. 18 FUNCTIONAL DESCRIPTION ......................................................................................... 19 MASTER CLOCK GENERATOR ...................................................................................................................... 19 Figure 4. Two Input Clock Source .................................................................................................. 19 Figure 5. One Input Clock Source .................................................................................................. 19 RECEIVER ........................................................................................................................ 20 RECEIVER INPUT ......................................................................................................................................... TABLE 1: MASTER CLOCK GENERATOR ............................................................................................... RECEIVE MONITOR MODE ........................................................................................................................... RECEIVER LOSS OF SIGNAL (RLOS) ........................................................................................................... Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ............... Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ......................... Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ............... RECEIVE HDB3/B8ZS DECODER ................................................................................................................ RECOVERED CLOCK (RCLK) SAMPLING EDGE ............................................................................................ Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ............................................... Figure 10. Receive Clock and Output Data Timing ....................................................................... JITTER ATTENUATOR .................................................................................................................................. GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................. TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ........................................ ARBITRARY PULSE GENERATOR FOR T1 AND E1 .......................................................................................... DIGITAL DATA FORMAT ............................................................................................................................... TRANSMIT CLOCK (TCLK) SAMPLING EDGE ................................................................................................ Figure 11. Arbitrary Pulse Segment Assignment .......................................................................... TRANSMIT HDB3/B8ZS ENCODER .............................................................................................................. Figure 12. Transmit Clock and Input Data Timing ........................................................................ TABLE 3: EXAMPLES OF HDB3 ENCODING ........................................................................................... TABLE 4: EXAMPLES OF B8ZS ENCODING ........................................................................................... DRIVER FAILURE MONITOR (DMO) .............................................................................................................. TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ...................................................................... TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ........................... 20 20 21 21 21 22 22 23 23 23 23 24 24 24 25 25 25 25 26 26 26 26 27 27 27 TRANSMITTER ................................................................................................................. 25 TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 29 RECEIVER (CHANNELS 0 - 3) ................................................................................................................... 29 Internal Receive Termination Mode .......................................................................................................... 29 TABLE 6: RECEIVE TERMINATION CONTROL .......................................................................................... 29 I XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY REV. P1.3.4 Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode ........ TABLE 7: RECEIVE TERMINATIONS ....................................................................................................... Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ............. TRANSMITTER (CHANNELS 0 - 3) ............................................................................................................ Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... TABLE 8: TRANSMIT TERMINATION CONTROL ....................................................................................... TABLE 9: TERMINATION SELECT CONTROL .......................................................................................... REDUNDANCY APPLICATIONS ............................................................................................................. TABLE 10: TRANSMIT TERMINATION CONTROL ..................................................................................... TABLE 11: TRANSMIT TERMINATIONS ................................................................................................... TYPICAL REDUNDANCY SCHEMES ..................................................................................................... Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ....... Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy ............. Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy ......................... Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy .......................... PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... TRANSMIT ALL ONES (TAOS) .................................................................................................................... NETWORK LOOP CODE DETECTION AND TRANSMISSION .............................................................................. TABLE 12: PATTERN TRANSMISSION CONTROL ..................................................................................... TABLE 13: LOOP-CODE DETECTION CONTROL ..................................................................................... TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... LOOP-BACK MODES ................................................................................................................................... LOCAL ANALOG LOOP-BACK (ALOOP) ....................................................................................................... TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE ........................................................................ TABLE 15: LOOP-BACK CONTROL IN HOST MODE ................................................................................. Figure 20. Local Analog Loop-back signal flow ........................................................................... REMOTE LOOP-BACK (RLOOP) ................................................................................................................. Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path ................. Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path .............. DIGITAL LOOP-BACK (DLOOP) .................................................................................................................. DUAL LOOP-BACK ...................................................................................................................................... Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ................ Figure 24. Signal flow in Dual loop-back mode ............................................................................ TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ........................................................... MICROPROCESSOR REGISTER TABLES ........................................................................................................ TABLE 17: MICROPROCESSOR REGISTER ADDRESS ............................................................................. TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION ................................................................. MICROPROCESSOR REGISTER DESCRIPTIONS ............................................................................................. TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION ........................................................... TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION ........................................................... TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION ........................................................... TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION ........................................................... TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION ........................................................... TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION ........................................................... TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION ........................................................... TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION ........................................................... TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION ........................................................... TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION ........................................................... TABLE 29: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION ......................................................... TABLE 30: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION ......................................................... TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION ......................................................... 29 30 30 31 31 31 31 32 32 32 33 34 34 35 36 37 37 37 37 37 38 39 39 39 39 39 40 40 40 41 41 41 41 42 43 43 43 46 46 47 49 51 53 54 56 57 58 58 59 59 60 Transmit Termination Mode ...................................................................................................................... 31 External Transmit Termination Mode ........................................................................................................ 31 MICROPROCESSOR PARALLEL INTERFACE .............................................................. 42 II XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY .......................................................... .......................................................... .......................................................... .......................................................... 60 61 61 62 TABLE 32: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION TABLE 33: MICROPROCESSOR REGISTER #14, BIT DESCRIPTION TABLE 34: MICROPROCESSOR REGISTER #15, BIT DESCRIPTION TABLE 35: MICROPROCESSOR REGISTER #64, BIT DESCRIPTION CLOCK SELECT REGISTER ........................................................................................... 63 Figure 25. Register 0x81h Sub Registers ...................................................................................... 63 TABLE 36: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION .......................................................... 64 TABLE 37: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION .......................................................... 65 ELECTRICAL CHARACTERISTICS ................................................................................ 67 TABLE 38: ABSOLUTE MAXIMUM RATINGS ........................................................................................... TABLE 39: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS ........................................ TABLE 40: XRT83L34 POWER CONSUMPTION .................................................................................... TABLE 41: E1 RECEIVER ELECTRICAL CHARACTERISTICS ..................................................................... TABLE 42: T1 RECEIVER ELECTRICAL CHARACTERISTICS ..................................................................... TABLE 43: E1 TRANSMIT RETURN LOSS REQUIREMENT ........................................................................ TABLE 44: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................... TABLE 45: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS ............................................................... Figure 26. ITU G.703 Pulse Template ............................................................................................. TABLE 46: TRANSMIT PULSE MASK SPECIFICATION .............................................................................. Figure 27. DSX-1 Pulse Template (normalized amplitude) ........................................................... TABLE 47: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS ........................................... TABLE 48: AC ELECTRICAL CHARACTERISTICS .................................................................................... Figure 28. Transmit Clock and Input Data Timing ........................................................................ MICROPROCESSOR INTERFACE I/O TIMING .................................................................................................. 67 67 67 68 69 69 70 70 71 71 72 72 73 73 74 Intel Interface Timing - Asynchronous ....................................................................................................... 74 Figure 29. Receive Clock and Output Data Timing ....................................................................... 74 Figure 30. Intel Asynchronous Programmed I/O Interface Timing .............................................. 74 TABLE 49: ASYNCHRONOUS MODE 1 - INTEL 8051 AND 80188 INTERFACE TIMING ............................... 75 Motorola Asychronous Interface Timing .................................................................................................... 76 Figure 31. Motorola 68K Asynchronous Programmed I/O Interface Timing .............................. 76 TABLE 50: ASYNCHRONOUS - MOTOROLA 68K - INTERFACE TIMING SPECIFICATION ............................. 76 Figure 32. Microprocessor Interface Timing - Reset Pulse Width ............................................... 76 ORDERING INFORMATION ............................................................................................. 77 PACKAGE DIMENSIONS - 14X20 MM, 128 PIN PACKAGE ................................................................................ 77 REVISIONS ................................................................................................................................................. 78 NOTES: ......................................................................................................................................... 79 III PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PIN DESCRIPTION BY FUNCTION RECEIVE SECTIONS SIGNAL NAME RLOS_0 PIN # 4 TYPE O DESCRIPTION Receiver Loss of Signal for Channel _0 This output signal goes `High' for at least one RCLK_0 cycle to indicate loss of signal at the receive 0 input. RLOS will remain "High" for the entire duration of the loss of signal detected by the receiver logic. See "Receiver Loss of Signal (RLOS)" on page 20. Receiver Loss of Signal for Channel _1 Receiver Loss of Signal for Channel _2 Receiver Loss of Signal for Channel _3 Receiver Clock Output for Channel _0 Receiver Clock Output for Channel _1 Receiver Clock Output for Channel _2 Receiver Clock Output for Channel _3 Receiver Negative Data Output for Channel _0 - Dual-Rail mode This signal is the receiver negative-rail output data. Line Code Violation Output for Channel _0 - Single-Rail mode This signal goes `High' for one RCLK_0 cycle to indicate a code violation is detected in the received data of Channel _0. If AMI coding is selected, every bipolar violation received will cause this pin to go "High". Receiver Negative Data Output for Channel _1 Line Code Violation Output for Channel _1 Receiver Negative Data Output for Channel _2 Line Code Violation Output for Channel _2 Receiver Negative Data Output for Channel _3 Line Code Violation Output for Channel _3 Receiver Positive Data Output for Channel _0 - Dual-Rail mode This signal is the receive positive-rail output data sent to the Framer. Receiver NRZ Data Output for Channel _0 - Single-Rail mode This signal is the receive output data. Receiver Positive Data Output for Channel _1 Receiver NRZ Data Output for Channel _1 Receiver Positive Data Output for Channel _2 Receiver NRZ Data Output for Channel _2 Receiver Positive Data Output for Channel _3 Receiver NRZ Data Output for Channel _3 RLOS_1 RLOS_2 RLOS_3 RCLK_0 RCLK_1 RCLK_2 RCLK_3 RNEG_0 LCV_0 28 75 99 5 27 76 98 6 O O RNEG_1 LCV_1 RNEG_1 LCV_2 RNEG_1 LCV_3 RPOS_0 26 77 97 7 O RDATA_0 RPOS_1 RDATA_1 RPOS_2 RDATA_2 RPOS_3 RDATA_3 RTIP_0 RTIP_1 RTIP_2 RTIP_3 25 78 96 9 23 80 94 I Receiver Differential Tip Positive Input for Channel _0 Positive differential receive input from the line. Receiver Differential Tip Positive Input for Channel _1 Receiver Differential Tip Positive Input for Channel _2 Receiver Differential Tip Positive Input for Channel _3 5 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY SIGNAL NAME RRING_0 RRING_1 RRING_2 RRING_3 RXMUTE PIN # 10 22 81 93 73 TYPE I DESCRIPTION Receiver Differential Ring Negative Input for Channel _0 Negative differential receive input from the line. Receiver Differential Ring Negative Input for Channel _1 Receiver Differential Ring Negative Input for Channel _2 Receiver Differential Ring Negative Input for Channel _3 Receive Muting - Hardware mode Connecting this pin `High' will mute (force to ground) the outputs RPOS_n/ RNEG_n when a LOS condition occurs, to prevent data chattering. This pin is internally pulled "low" consequently muting is normally disabled. I NOTES: 1. Internally pulled "Low" with 50k resistor. 2. In Hardware mode, all receive channels share the same RXMUTE control function. RDY_DTACK 73 O Ready Output (Data Transfer Acknowledge Output) - Host mode See "Ready Output (Data Transfer Acknowledge Output) - Host Mode" on page 9. Receive External Resistor Control Pins - Hardware mode Receive External Resistor Control Pin 0 Receive External Resistor Control Pin 1 These pins are used to determine the value of the external Receive fixed resistor according to the following table: Required Fixed External RX Resistor No External Fixed Resistor 240 210 150 RXRES0 RXRES1 108 109 I RXRES1 0 0 1 1 RXRES0 0 1 0 1 NOTE: These pins are internally pulled "Low" with 50k resistor. RCLKE 106 I Receive Clock Edge - Hardware Mode Set this pin "High" to sample RPOS_N/RNEG_n on the falling edge of RCLK_n. With this pin tied "Low", output data are updated on the rising edge of RCLK_n. Microprocessor Type Select Input pin 1 - Host mode This pin along with PTS2 (pin 107) is used to select the microprocessor type. See "Microprocessor Type Select Input Pins - Host Mode:" on page 10. PTS1 NOTE: This pin is internally pulled "Low" with a 50k resistor. 6 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TRANSMITTER SECTIONS SIGNAL NAME TCLKE PIN # 107 TYPE I DESCRIPTION Transmit Clock Edge - Hardware Mode With this pin set to a "High", transmit input data of all channels are sampled at the rising edge of TCLK_n. With this pin tied "Low", input data are sampled at the falling edge of TCLK_n. Microprocessor Type Select Input pin 2 - Host Mode This pin along with PTS1 (pin 106) selects the microprocessor type. See "Microprocessor Type Select Input Pins - Host Mode:" on page 10. PTS2 NOTE: This pin is internally pulled "Low" with a 50k resistor. TTIP_0 TTIP_1 TTIP_2 TTIP_3 TRING_0 TRING_1 TRING_2 TRING_3 TPOS_0 TDATA_0 TPOS_1 TDATA_1 TPOS_2 TDATA_2 TPOS_3 TDATA_3 127 104 101 13 19 84 90 15 17 86 88 2 I O O Transmitter Tip Output for Channel _0 Positive differential transmit output to the line. Transmitter Tip Output for Channel _1 Transmitter Tip Output for Channel _2 Transmitter Tip Output for Channel _3 Transmitter Ring Output for Channel _0 Negative differential transmit output to the line. Transmitter Ring Output for Channel _1 Transmitter Ring Output for Channel _2 Transmitter Ring Output for Channel _3 Transmitter Positive Data Input for Channel _0 - Dual-rail mode This signal is the positive-rail input data for transmitter 0. Transmitter 0 Data Input - Single-Rail mode This pin is used as the NRZ input data for transmitter 0. Transmitter Positive Data Input for Channel _1 Transmitter 1 Data Input Transmitter Positive Data Input for Channel _2 Transmitter 2 Data Input Transmitter Positive Data Input for Channel _3 Transmitter 3 Data Input NOTE: Internally pulled "Low" with a 50k resistor for each channels. TNEG_0 3 I Transmitter Negative NRZ Data Input for Channel _0 Dual-Rail mode This signal is the negative-rail input data for transmitter 0. Single-Rail mode This pin can be left unconnected. Coding Select for Channel _0 - Hardware mode and Single-Rail mode Connecting this pin "Low" enables HDB3 in E1 or B8ZS in T1 encoding and decoding for Channel _0. Connecting this pin "High" selects AMI data format. Transmitter Negative NRZ Data Input for Channel _1 Coding Select for Channel _1 Transmitter Negative NRZ Data Input for Channel _2 Coding Select for Channel _2 Transmitter Negative NRZ Data Input for Channel _3 Coding Select for Channel _3 CODES_0 TNEG_1 CODES_1 TNEG_2 CODES_2 TNEG_3 CODES_3 126 105 100 NOTE: Internally pulled "Low" with a 50k resistor for channel _n 7 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY SIGNAL NAME TCLK_0 PIN # 1 TYPE I DESCRIPTION Transmitter Clock Input for Channel _0 - Host mode and Hardware mode E1 rate at 2.048MHz 50ppm. T1 rate at 1.544MHz 32ppm. During normal operation TCLK_0 is used for sampling input data at TPOS_0/ TDATA_0 and TNEG_0/CODES_0 while MCLK is used as the timing reference for the transmit pulse shaping circuit. Transmitter Clock Input for Channel _1 Transmitter Clock Input for Channel _2 Transmitter Clock Input for Channel _3 TCLK_1 TCLK_2 TCLK_3 TAOS_0 128 103 102 69 I NOTE: Internally pulled "Low" with a 50k resistor for all channels. Transmit All Ones for Channel _0 - Hardware mode Setting this pin "High" enables the transmission of an "All Ones" Pattern from Channel _0. A "Low" level stops the transmission of the "All Ones" Pattern. Transmit All Ones for Channel _1 Transmit All Ones for Channel _2 Transmit All Ones for Channel _3 Host mode: these pins act as various microprocessor functions. See "Microprocessor Interface" on page 9. TAOS_1 TAOS_2 TAOS_3 WR_R/W RD_DS ALE_AS CS TXON_0 70 71 72 69 70 71 72 122 I NOTE: These pins are internally pulled "Low" with a 50k resistor. Transmitter Turn On for Channel _0 Hardware mode Setting this pin "High" turns on the Transmit Section of Channel _0 and has no control of the Channel_0 receiver. When TXON_0 = "0" then TTIP_0 and TRING_0 driver outputs will be tri-stated. NOTE: In Hardware mode only, all receiver channels will be turned on upon power-up and there is no provision to power them off. The receive channels can only be independently powered on or off in Host mode. In Host mode The TXON_n bits in the channel control registers turn each channel Transmit section ON or OFF. However, control of the on/off function can be transferred to the Hardware pins by setting the TXONCTL bit (bit 6) to "1" in the register at address hex 0x42. Transmitter Turn On for Channel _1 Transmitter Turn On for Channel _2 Transmitter Turn On for Channel _3 TXON_1 TXON_2 TXON_3 123 124 125 NOTE: Internally pulled "Low" with a 50k resistor for all channels. 8 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 MICROPROCESSOR INTERFACE SIGNAL NAME HW_HOST PIN # 68 TYPE I DESCRIPTION Mode Control Input This pin selects Hardware or Host mode. Leave this pin unconnected or tie "High" to select Hardware mode. For Host mode, this pin must be tied "Low". NOTE: Internally pulled "High" with a 50k resistor. WR_R/W 69 I Write Input (Read/Write) - Host mode Intel bus timing: A "Low" pulse on WR selects a write operation when CS pin is "Low". Motorola bus timing: A "High" pulse on R/W selects a read operation and a "Low" pulse on R/W selects a write operation when CS is "Low". Transmit All "Ones" Channel_0 - Hardware Mode See "Transmit All Ones for Channel _0 - Hardware mode" on page 8. TAOS_0 69 NOTE: Internally pulled "Low" with a 50k resistor. RD_DS 70 I Read Input (Data Strobe) - Host Mode Intel bus timing: A "Low" pulse on RD selects a read operation when the CS pin is "Low". Motorola bus timing: A "Low" pulse on DS indicates a read or write operation when the CS pin is "Low". Transmit All "Ones" Channel_1 - Hardware Mode See "Transmit All Ones for Channel _0 - Hardware mode" on page 8. TAOS_1 70 NOTE: Internally pulled "Low" with a 50k resistor. ALE_AS 71 I Address Latch Input (Address Strobe) - Host Mode Intel bus timing: The address inputs are latched into the internal register on the falling edge of ALE. Motorola bus timing: The address inputs are latched into the internal register on the falling edge of AS. Transmit All "Ones" Channel_2 - Hardware Mode See "Transmit All Ones for Channel _0 - Hardware mode" on page 8. TAOS_2 71 NOTE: Internally pulled "Low" with a 50k resistor. CS TAOS_3 72 72 I Chip Select Input - Host Mode This signal must be "Low" in order to access the parallel port. Transmit All "Ones" Channel_3 - Hardware Mode See "Transmit All Ones for Channel _0 - Hardware mode" on page 8. NOTE: Internally pulled "Low" with a 50k resistor. RDY_DTACK 73 O Ready Output (Data Transfer Acknowledge Output) - Host Mode Intel bus timing: RDY is asserted "High" to indicate the device has completed a read or write operation. Motorola bus timing: DTACK is asserted "Low" to indicate the device has completed a read or write cycle. Receive Muting - Hardware mode See "Receive Muting - Hardware mode" on page 6. RXMUTE 73 I NOTE: Internally pulled "Low" with a 50k resistor. 9 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY SIGNAL NAME PTS1 PTS2 PIN # TYPE DESCRIPTION Microprocessor Type Select Input Pins - Host Mode: Microprocessor Type Select Input Bit 1 Microprocessor Type Select Input Bit 2 PTS2 PTS1 P T yp e 106 107 I 0 0 1 1 0 1 0 1 68H C 11, 8051, 80C 188 (async.) M otorola 68K (async.) Inte l x86 (sync.) M otorola 860 (sync.) RCLKE TCLKE 106 107 Receive Clock Edge select - Hardware mode See "Receive Clock Edge - Hardware Mode" on page 6. Transmit Clock Edge select - Hardware mode See "Transmit Clock Edge - Hardware Mode" on page 7. NOTE: These pins are internally pulled "Low" with a 50k resistor. Microprocessor Read/Write Data Bus Pins - Host Mode Data Bus[7] Data Bus[6] Data Bus[5] Data Bus[4] Data Bus[3] Data Bus[2] Data Bus[1] Data Bus[0] Loop-back Control pin, Bits [1:0]_Channel_n - Hardware Mode Pins 42 - 49 control which Loop-Back mode is selected per channel. See "Loop-Back Control Pins - Hardware Mode:" on page 15. D[7] D[6] D[5] D[4] D[3] D[2]/ D[1]/ D[0]/ LOOP1_0 LOOP0_0 LOOP1_1 LOOP0_1 LOOP1_2 LOOP0_2 LOOP1_3 LOOP0_3 PCLK 42 43 44 45 46 47 48 49 42 43 44 45 46 47 48 49 50 I/O NOTE: Internally pulled "Low" with a 50k resistor. I Microprocessor Clock Input - Host Mode Input clock for synchronous microprocessor operation. Maximum clock rate is 54 MHz. NOTE: This pin is internally pulled "Low" for asynchronous microprocessor interface when no clock is present. ATAOS Automatic Transmit "All Ones" - Hardware mode This pin functions as an Automatic Transmit "All Ones". See "Automatic Transmit "All Ones" Pattern - Hardware Mode" on page 14. 10 PRELIMINARY SIGNAL NAME XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PIN # TYPE DESCRIPTION Microprocessor Address Pins - Host mode: Microprocessor Interface Address Bus[6] Microprocessor Interface Address Bus[5] Microprocessor Interface Address Bus[4] Microprocessor Interface Address Bus[3] Microprocessor Interface Address Bus[2] Microprocessor Interface Address Bus[1] Microprocessor Interface Address Bus[0] Jitter Attenuator Select Pins - Hardware Mode Jitter Attenuator select pin 1 Jitter Attenuatore select pin 0 See "Jitter Attenuator" on page 12. Equalizer Control Pins - Hardware Mode Equalizer Control Input pin 4 Equalizer Control Input pin 3 Equalizer Control Input pin 2 Equalizer Control Input pin 1 Equalizer Control Input pin 0 Pins EQC[4:0] select the Receive Equalizer and Transmitter Line Build Out. See "Alarm Function//Redundancy Support" on page 14. A[6] A[5] A[4] A[3] A[2] A[1] A[0] JASEL1 JASEL0 57 58 59 60 61 62 63 57 58 I EQC4 EQC3 EQC2 EQC1 EQC0 59 60 61 62 63 NOTE: Internally pulled "Low" with a 50k resistor. INT 119 I Interrupt Output - Host Mode This pin goes "Low" to indicate an alarm condition has occurred within the device. Interrupt generation can be globally disabled by setting the GIE bit to "0" in the command control register. Transmitter Transformer Ratio Select - Hardware mode The function of this pin is to select the transmitter transformer ratio. See "Alarm Function//Redundancy Support" on page 14. TRATIO 119 NOTE: This pin is an open drain output and requires an external 10k pullup resistor. 11 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY JITTER ATTENUATOR SIGNAL NAME PIN # TYPE DESCRIPTION Jitter Attenuator Select Pins - Hardware Mode Jitter Attenuator select pin 0 Jitter Attenuator select pin 1 JASEL[1:0] pins are used to place the jitter attenuator in the transmit path, the receive path or to disable it. JA BW Hz JA BW T1 MHz E1 ----T1 3 3 3 ----E1 10 10 1.5 JASEL0 JASEL1 58 57 I JASEL1 0 0 1 0 1 0 A[6] A[5] 57 58 JASEL0 0 1 0 0 1 1 JA Path Disabled Transmit Receive Receive FIFO Size T1/E1 -------32/32 32/32 64/64 Microprocessor Address Bits A[6:5] -Host Mode See "Microprocessor Address Pins - Host mode:" on page 11. NOTE: Internally pulled "Low" with a 50k resistor. 12 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 CLOCK SYNTHESIZER SIGNAL NAME MCLKE1 PIN # 32 TYPE I DESCRIPTION E1 Master Clock Input A 2.048MHz clock for with an accuracy of better than 50ppm and a duty cycle of 40% to 60% can be provided at this pin. In systems that have only one master clock source available (E1 or T1), that clock should be connected to both MCLKE1 and MCLKT1 inputs for proper operation. NOTES: 1. All channels of the XRT83L34 must be operated at the same clock rate, either T1, E1 or J1. 2. Internally pulled "Low" with a 50k resistor. CLKSEL0 CLKSEL1 CLKSEL2 37 38 39 I Clock Select inputs for Master Clock Synthesizer - Hardware mode CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be used to generate a master clock from an accurate external clock source according to the following table. The MCLKRATE control signal is generated from the state of EQC[4:0] inputs. See Table 4 for description of Transmit Equalizer Control bits. Host Mode: The state of these pins are ignored and the master frequency PLL is controlled by the corresponding interface bits. See Table 35, register address 1000001. MCLKE1 (kHz) 2048 2048 2048 1544 1544 2048 8 8 16 16 56 56 64 64 128 128 256 256 MCLKT1 (kHz) 2048 2048 1544 1544 1544 1544 X X X X X X X X X X X X CLKSEL2 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CLKSEL1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CLKSEL0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MCLKRATE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLKOUT (KHz) 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 NOTE: These pins are internally pulled "Low" with a 50k resistor. 13 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY SIGNAL NAME MCLKT1 PIN # 33 TYPE I DESCRIPTION T1 Master Clock Input This signal is an independent 1.544MHz clock for T1 systems with required accuracy of better than 50ppm and duty cycle of 40% to 60%. MCLKT1 input is used in the T1 mode. NOTES: 1. All channels of the XRT83L34 must be operated at the same clock rate, either T1, E1 or J1. 2. See pin 32 description for further explanation for the usage of this pin. 3. Internally pulled "Low" with a 50k resistor. MCLKOUT 36 O Synthesized Master Clock Output This signal is the output of the Master Clock Synthesizer PLL which is at T1 or E1 rate based upon the mode of operation. ALARM FUNCTION//REDUNDANCY SUPPORT SIGNAL NAME GAUGE PIN # 87 TYPE I DESCRIPTION Twisted Pair Cable Wire Gauge Select - Hardware mode Connect this pin "High" to select 26 Gauge wire. Connect this pin "Low" to select 22 and 24 gauge wire for all channels. NOTE: Internally pulled "Low" with a 50k resistor. DMO_0 64 O Driver Failure Monitor Channel _0 This pin transitions "High" if a short circuit condition is detected in the transmit driver of Channel _0, or no transmit output pulse is detected for more than 128 TCLK_0 cycles. Driver Failure Monitor Channel _1 Driver Failure Monitor Channel _2 Driver Failure Monitor Channel _3 Automatic Transmit "All Ones" Pattern - Hardware Mode A "High" level on this pin enables the automatic transmission of an "All Ones" AMI pattern from the transmitter of any channel that the receiver of that channel has detected an LOS condition. A "Low" level on this pin disables this function. DMO_1 DMO_2 DMO_3 ATAOS 65 66 67 50 I NOTE: All channels share the same ATAOS input control function. PCLK Microprocessor Clock Input - Host Mode See "Microprocessor Clock Input - Host Mode" on page 10. NOTE: This pin is internally pulled "Low" for asynchronous microprocessor interface when no clock is present. 14 PRELIMINARY SIGNAL NAME TRATIO XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PIN # 119 TYPE I DESCRIPTION Transmitter Transformer Ratio Select - Hardware Mode In external termination mode (TXSEL = 0), setting this pin "High" selects a transformer ratio of 1:2 for the transmitter. A "Low" on this pin sets the transmitter transformer ratio to 1:2.45. In the internal termination mode the transmitter transformer ratio is permanently set to 1:2 and the state of this pin is ignored. Interrupt Output - Host Mode This pin is asserted "Low" to indicate an alarm condition. See "Microprocessor Interface" on page 9. INT O NOTE: This pin is an open drain output and requires an external 10k pullup resistor. RESET 121 I Hardware Reset (Active "Low") When this pin is tied "Low" for more than 10s, the device is put in the reset state. Pulling RESET and ICT pins "Low" simultaneously will put the chip in factory test mode. This condition should not be permitted during normal operation. NOTE: Internally pulled "High" with a 50k resistor. SR/DR 16 I Single-Rail/Dual-Rail Data Format Connect this pin "Low" to select transmit and receive data format in Dual-rail mode. In this mode, HDB3 or B8ZS encoder and decoder are not available. Connect this pin "High" to select single-rail data format. NOTE: Internally pulled "Low" with a 50k resistor. Loop-Back Control Pins - Hardware Mode: Loop-back control pin 1 - Channel _0 Loop-back control pin 0 - Channel _0 Loop-back control pin 1 - Channel _1 Loop-back control pin 0 - Channel _1 Loop-back control pin 1 - Channel _2 Loop-back control pin 0 - Channel _2 Loop-back control pin 1 - Channel _3 Loop-back control pin 0 - Channel _3 LOOP1_n 0 0 1 1 D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] 42 43 44 45 46 47 48 49 LOOP0_n 0 1 0 1 MODE Normal Mode No Loop-back Channel_n Local Loop-Back Channel_n Remote Loop-Back Channel_n Digital Loop-Back Channel_n LOOP1_0 LOOP0_0 LOOP1_1 LOOP0_1 LOOP1_2 LOOP0_2 LOOP1_3 LOOP0_3 42 43 44 45 46 47 48 49 I/O Microprocessor R/W Data bits [7:0] - Host Mode These pins are microprocessor data bus pins. See "Microprocessor Read/ Write Data Bus Pins - Host Mode" on page 10. NOTE: These pins are internally pulled "Low" with a 50k resistor. 15 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY SIGNAL NAME EQC4 PIN # 59 TYPE I DESCRIPTION Equalizer Control Input 4 - Hardware Mode This pin together with EQC[3:0] are used for controlling the transmit pulse shaping, transmit line build-out (LBO), receive monitoring and also to select T1, E1 or J1 Modes of operation. See Table 4 for description of Transmit Equalizer Control bits. Equalizer Control Input 3 Equalizer Control Input 2 Equalizer Control Input 1 Equalizer Control Input 0 EQC3 EQC2 EQC1 EQC0 60 61 62 63 NOTES: 1. In Hardware mode all transmit channels share the same pulse setting controls function. A[4] A[3] A[2] A[1] A[0] RXTSEL 59 60 61 62 63 110 I 2. All channels of an XRT83L34 must operate at the same clock rate, either the T1, E1 or J1 modes. Microprocessor Address bits [4:0] - Host Mode See "Microprocessor Address Pins - Host mode:" on page 11. NOTE: Internally pulled "Low" with a 50k resistor for all channels. Receiver Termination Select In Hardware mode, when this pin is "Low" the receive line termination is determined only by the external resistor. When "High", the receive termination is realized by internal resistors or the combination of internal and external resistors. These conditions are described in the table below. NOTE: In Hardware mode all channels share the same RXTSEL control function. RXTSEL 0 1 RX Termination External Internal In Host mode, the RXTSEL_n bits in the channel control registers determines if the receiver termination is external or internal. However the function of RXTSEL can be transferred to the Hardware pin by setting the TERCNTL bit (bit 4) to "1" in the register 66 address hex 0x42. NOTE: Internally pulled "Low" with a 50k resistor. TXTSEL 111 I Transmit Termination Select - Hardware Mode When this pin is "Low" the transmit line termination is determined only by an external resistor. When "High", the transmit termination is realized only by the internal resistor. TXTSEL 0 1 TX Termination External Internal NOTES: 1. This pin is internally pulled "Low" with a 50k resistor. 2. In Hardware Mode all channels share the same TXTSEL control function. 16 PRELIMINARY SIGNAL NAME TERSEL0 TERSEL1 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PIN # 113 112 TYPE I DESCRIPTION Termination Impedance Select pin 0 Termination Impedance Select pin 1 In the Hardware mode and in the internal termination mode (TXTSEL="1" and RXTSEL="1"), TERSEL[1:0] control the transmit and receive termination impedance according to the following table. TERSEL1 0 0 1 1 TERSEL0 0 1 0 1 Termination 100 110 75 120 In the internal termination mode, the receiver termination of each receiver is realized completely by internal resistors or by the combination of internal and one fixed external resistor (see description of RXRES[1:0] pins). In the internal termination mode the transformer ratio of 1:2 and 1:1 is required for transmitter and receiver respectively with the transmitter output AC coupled to the transformer. NOTES: 1. This pin is internally pulled "Low" with a 50k resistor. 2. In Hardware Mode all channels share the same TERSEL control function. ICT 120 I In-Circuit Testing (active "Low"): When this pin is tied "Low", all output pins are forced to a "High" impedance state for in-circuit testing. Pulling RESET and ICT pins "Low" simultaneously will put the chip in factory test mode. This condition should not be permitted during normal operation. NOTE: Internally pulled "High" with a 50k resistor. 17 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY POWER AND GROUND SIGNAL NAME TGND_0 TGND_1 TGND_2 TGND_3 TVDD_0 TVDD_1 TVDD_2 TVDD_3 RVDD_0 RVDD_1 RVDD_2 RVDD_3 RGND_0 RGND_1 RGND_2 RGND_3 VDDPLL_1 VDDPLL_2 AVDD GNDPLL_1 GNDPLL_2 AGND DVDD DVDD DVDD DVDD DVDD DVDD DGND DGND DGND DGND GND DGND DGND PIN # 12 20 83 91 14 18 85 89 8 24 79 95 11 21 82 92 30 31 40 34 35 41 29 51 52 53 115 116 54 55 56 74 114 117 118 TYPE **** DESCRIPTION Transmitter Analog Ground for Channel _0 Transmitter Analog Ground for Channel _1 Transmitter Analog Ground for Channel _2 Transmitter Analog Ground for Channel _3 Transmitter Analog Positive Supply (3.3V + 5%) for Channel _0 Transmitter Analog Positive Supply (3.3V + 5%) for Channel _1 Transmitter Analog Positive Supply (3.3V + 5%) for Channel _2 Transmitter Analog Positive Supply (3.3V + 5%) for Channel _3 Receiver Analog Positive Supply (3.3V 5%) for Channel _0 Receiver Analog Positive Supply (3.3V 5%) for Channel _1 Receiver Analog Positive Supply (3.3V 5%) for Channel _2 Receiver Analog Positive Supply (3.3V 5%) for Channel _3 Receiver Analog Ground for Channel _0 Receiver Analog Ground for Channel _1 Receiver Analog Ground for Channel _2 Receiver Analog Ground for Channel _3 Analog Positive Supply for Master Clock Synthesizer PLL (3.3V 5%) Analog Positive Supply for Master Clock Synthesizer PLL (3.3V 5%) Analog Positive Supply (3.3V 5%) Analog Ground for Master Clock Synthesizer PLL Analog Ground for Master Clock Synthesizer PLL Analog Ground Digital Positive Supply (3.3V 5%) Digital Positive Supply (3.3V 5%) Digital Positive Supply (3.3V 5%) Digital Positive Supply (3.3V 5%) Digital Positive Supply (3.3V 5%) Digital Positive Supply (3.3V 5%) Digital Ground Digital Ground Digital Ground Digital Ground Ground Digital Ground Digital Ground **** **** **** **** **** **** **** 18 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 FUNCTIONAL DESCRIPTION The XRT83L34 is a fully integrated four-channel long-haul and short-haul transceiver intended for T1, J1 or E1 systems. Simplified block diagrams of the device are shown in Figure 1, Host mode and Figure 2, Hardware mode. The XRT83L34 can receive signals that have been attenuated from 0 to 36dB at 772kHz (0 to 6000 feet cable loss) for T1 and from 0 to 43dB at 1024kHz for E1 systems. In T1 applications, the XRT83L34 can generate five transmit pulse shapes to meet the short-haul Digital Crossconnect (DSX-1) template requirement as well as four CSU Line Build-Out (LBO) filters of 0dB, -7.5dB, -15dB and -22.5dB as required by FCC rules. It also provides programmable transmit output pulse generators for each channel that can be used for output pulse shaping allowing performance improvement over a wide variety of conditions. The operation and configuration of the XRT83L34 can be controlled through a parallel microprocessor Host interface or, by Hardware control. MASTER CLOCK GENERATOR Using a variety of external clock sources, the on-chip frequency synthesizer generates the T1 (1.544MHz) or E1 (2.048MHz) master clocks necessary for the transmit pulse shaping and receive clock recovery circuit. There are two master clock inputs MCLKE1 and MCLKT1. In systems where both T1 and E1 master clocks are available these clocks can be connected to the respective pins. All channels of a given XRT83L34 must be operated at the same clock rate, either T1, E1 or J1 modes. In systems that have only one master clock source available (E1 or T1), that clock should be connected to both MCLKE1 and MCLKT1 inputs for proper operation. T1 or E1 master clocks can be generated from 8kHz, 16kHz, 56kHz, 64kHz, 128kHz and 256kHz external clocks under the control of CLKSEL[2:0] inputs according to Table 1. NOTE: EQC[4:0] determine the T1/E1 operating mode. See Table 5 for details. FIGURE 4. TWO INPUT CLOCK SOURCE Two Input Clock Sources 2.048MHz +/-50ppm 1.544MHz +/-50ppm MCLKE1 MCLKOUT MCLKT1 1.544MHz or 2.048MHz FIGURE 5. ONE INPUT CLOCK SOURCE Input Clock Options 8kHz 16kHz 56kHz 64kHz 128kHz 256kHz 1.544MHz 2.048MHz One Input Clock Source MCLKE1 MCLKOUT MCLKT1 1.544MHz or 2.048MHz 19 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 1: MASTER CLOCK GENERATOR MCLKE1 KHZ MCLKT1 KHZ CLKSEL2 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CLKSEL1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CLKSEL0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MCLKRATE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MASTER CLOCK KHZ 2048 2048 2048 1544 1544 2048 8 8 16 16 56 56 64 64 128 128 256 256 2048 2048 1544 1544 1544 1544 x x x x x x x x x x x x 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 In Host mode the programming is achieved through the corresponding interface control bits, the state of the CLKSEL[2:0] control bits and the state of the MCLKRATE interface control bit. RECEIVER RECEIVER INPUT At the receiver input, a cable attenuated AMI signal can be coupled to the receiver through a capacitor or a 1:1 transformer. The input signal is first applied to a selective equalizer for signal conditioning. The maximum equalizer gain is up to 36dB for T1 and 43dB for E1 modes. The equalized signal is subsequently applied to a peak detector which in turn controls the equalizer settings and the data slicer. The slicer threshold for both E1 and T1 is typically set at 50% of the peak amplitude at the equalizer output. After the slicers, the digital representation of the AMI signals are applied to the clock and data recovery circuit. The recovered data subsequently goes through the jitter attenuator and decoder (if selected) for HDB3 or B8ZS decoding before being applied to the RPOS_n/RDATA_n and RNEG_n/LCV_n pins. Clock recovery is accomplished by a digital phase-locked loop (DPLL) which does not require any external components and can tolerate high levels of input jitter that meets or exceeds the ITU-G.823 and TR-TSY000499 standards. In Hardware mode only, all receive channels are turned on upon power-up and are always on. In Host mode, ach receiver channel can be individually turned on or off with the respective channel RXON_n bit. See "Microprocessor Register #0, Bit Description" on page 46. 20 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 RECEIVE MONITOR MODE In applications where Monitor mode is desired, the equalizer can be configured in a gain mode which handles input signals attenuated resistively up to 29dB, along with 0 to 6dB cable attenuation for both T1 and E1 applications, refer to Table 5 for details. This feature is available in both Hardware and Host modes. RECEIVER LOSS OF SIGNAL (RLOS) For compatibility with ITU G.775 requirements, the RLOS monitoring function is implemented using both analog and digital detection schemes. If the analog RLOS condition occurs, a digital detector is activated to count for 32 consecutive zeros in E1 (4096 bits in Extended Los mode, EXLOS = "1") or 175 consecutive zeros in T1 before RLOS is asserted. RLOS is cleared when the input signal rises +3dB (built in hysteresis) above the point at which it was declared and meets 12.5% ones density of 4 ones in a 32 bit window, with no more than 16 consecutive zeros for E1. In T1 mode, RLOS is cleared when the input signal rises +3dB (built in hysteresis) above the point at which it was declared and contains 16 ones in a 128 bit window with no more than 100 consecutive zeros in the data stream. When loss of signal occurs, RLOS register indication and register status will change. If the RLOS register enable is set high (enabled), the alarm will trigger an interrupt causing the interrupt pin (INT) to go low. Once the alarm status register has been read, it will automatically reset upon read (RUR), and the INT pin will return high. Analog RLOS Setting the Receiver Inputs to -15dB T1/E1 Short Haul Mode By setting the receiver inputs to -15dB T1/E1 short haul mode, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +15dB normalizing the T1/E1 input signal. NOTE: This is the only setting that refers to cable loss (frequency), not flat loss (resistive). Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+15dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is typically -24dB (-15dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable attenuation of -21dB. See Figure 6 for a simplified diagram. FIGURE 6. SIMPLIFIED DIAGRAM OF -15dB T1/E1 SHORT HAUL MODE AND RLOS CONDITION Norm alized up to +15dB Max -9dB Clear LOS +3dB Declare LOS Declare LOS +3dB Clear LOS -9dB Norm alized up to +15dB Max Setting the Receiver Inputs to -29dB T1/E1 Gain Mode By setting the receiver inputs to -29dB T1/E1 gain mode, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +29dB normalizing the T1/E1 input signal. NOTE: This is the only setting that refers to flat loss (resistive). All other modes refer to cable loss (frequency). Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+29dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is 21 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY typically -38dB (-29dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total flat loss of -35dB. See Figure 7 for a simplified diagram. FIGURE 7. SIMPLIFIED DIAGRAM OF -29dB T1/E1 GAIN MODE AND RLOS CONDITION Norm alized up to +29dB Max -9dB Clear LOS +3dB Declare LOS Declare LOS +3dB Clear LOS -9dB Norm alized up to +29dB Max Setting the Receiver Inputs to -36dB T1/E1 Long Haul Mode By setting the receiver inputs to -36dB T1/E1 long haul mode, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +36dB normalizing the T1 input signal. This setting refers to cable loss (frequency), not flat loss (resistive). Once the T1/E1 input signal has been normalized to 0dB by adding the maximum gain (+36dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB. The total cable loss at RLOS declaration is typically -45dB (-36dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable attenuation of -42dB. See Figure 8 for a simplified diagram. FIGURE 8. SIMPLIFIED DIAGRAM OF -36dB T1/E1 LONG HAUL MODE AND RLOS CONDITION Norm alized up to +36dB Max -9dB Clear LOS +3dB Declare LOS Declare LOS +3dB Clear LOS -9dB Norm alized up to +36dB Max E1 Extended RLOS E1: Setting the Receiver Inputs to Extended RLOS By setting the receiver inputs to extended RLOS, the equalizer will detect the incoming amplitude and make adjustments by adding gain up to a maximum of +43dB normalizing the E1 input signal. This setting refers to cable loss (frequency), not flat loss (resistive). Once the E1 input signal has been normalized to 0dB by adding the maximum gain (+43dB), the receiver will declare RLOS if the signal is attenuated by an additional -9dB. 22 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 The total cable loss at RLOS declaration is typically -52dB (-43dB + -9dB). A 3dB hysteresis was designed so that transients will not trigger the RLOS to clear. Therefore, the RLOS will typically clear at a total cable attenuation of -49dB. See Figure 9 for a simplified diagram. FIGURE 9. SIMPLIFIED DIAGRAM OF EXTENDED RLOS MODE (E1 ONLY) Norm alized up to +45dB Max -9dB Clear LOS +3dB Declare LOS Declare LOS +3dB Clear LOS -9dB Norm alized up to +45dB Max RECEIVE HDB3/B8ZS DECODER The Decoder function is available in both Hardware and Host modes on a per channel basis by controlling the TNEG_n/CODES_n pin or the CODES_n interface bit. The decoder function is only active in single-rail Mode. When selected, receive data in this mode will be decoded according to HDB3 rules for E1 and B8ZS for T1 systems. Bipolar violations that do not conform to the coding scheme will be reported as Line Code Violation at the RNEG_n/LCV_n pin of each channel. The length of the LCV pulse is one RCLK cycle for each code violation. In E1mode only, an excessive number of zeros in the receive data stream is also reported as an error at the same output pin. If AMI decoding is selected in single rail mode, every bipolar violation in the receive data stream will be reported as an error at the RNEG_n/LCV_n pin. RECOVERED CLOCK (RCLK) SAMPLING EDGE This feature is available in both Hardware and Host modes on a global basis. In Host mode, the sampling edge of RCLK output can be changed through the interface control bit RCLKE. If a "1" is written in the RCLKE interface bit, receive data output at RPOS_n/RDATA_n and RNEG_n/LCV_n are updated on the falling edge of RCLK for all eight channels. Writing a "0" to the RCLKE register, updates the receive data on the rising edge of RCLK. In Hardware mode the same feature is available under the control of the RCLKE pin. FIGURE 10. RECEIVE CLOCK AND OUTPUT DATA TIMING RDY RCLKR RCLKF RCLK RPOS or RNEG RHO 23 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY JITTER ATTENUATOR To reduce phase and frequency jitter in the recovered clock, the jitter attenuator can be placed in the receive signal path. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth that can vary between 2x32 and 2x64. The jitter attenuator can also be placed in the transmit signal path or disabled altogether depending upon system requirements. The jitter attenuator, other than using the master clock as reference, requires no external components. With the jitter attenuator selected, the typical throughput delay from input to output is 16 bits for 32 bit FIFO size or 32 bits for 64 bit FIFO size. When the read and write pointers of the FIFO in the jitter attenuator are within two bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside the two bits window. Under normal condition, the jitter transfer characteristic meets the narrow bandwidth requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards. In T1 mode the Jitter Attenuator Bandwidth is always set to 3Hz. In E1 mode, the bandwidth can be reduced through the JABW control signal. When JABW is set "High" the bandwidth of the jitter attenuator is reduced from 10Hz to 1.5Hz. Under this condition the FIFO length is automatically set to 64 bits and the 32 bits FIFO length will not be available in this mode. Jitter attenuator controls are available on a per channel basis in the Host mode and on a global basis in the Hardware mode. GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) The XRT83L34 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are removed which can leave gaps in the incoming data stream. If the jitter attenuator is enabled in the transmit path, the 32-Bit or 64-Bit FIFO is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap width of the 8-Channel LIU is shown in Table 2. TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS FIFO DEPTH 32-Bit 64-Bit MAXIMUM GAP WIDTH 20 UI 50 UI NOTE: If the LIU is used in a loop timing system, the jitter attenuator should be enabled in the receive path. 24 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 ARBITRARY PULSE GENERATOR FOR T1 AND E1 The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit binary word by programming the appropriate channel register. This allows the system designer to set the overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit is set to "1", the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is set to "0", the segment will move in a negative direction relative to a flat line condition. A pulse with numbered segments is shown in Figure 11. FIGURE 11. ARBITRARY PULSE SEGMENT ASSIGNMENT 1 2 3 Segment 1 2 3 4 5 6 7 8 Register 0xn8 0xn9 0xna 0xnb 0xnc 0xnd 0xne 0xnf 4 8 7 6 5 NOTE: By default, the arbitrary segments are programmed to 0x00h. The transmitter outputs will result in an all zero pattern to the line. TRANSMITTER DIGITAL DATA FORMAT Both the transmitter and receiver can be configured to operate in dual or single-rail data formats. This feature is available under both Hardware and Host control modes, on a global basis. The dual or single-rail data format is determined by the state of the SR/DR pin in Hardware mode or SR/DR interface bit in the Host mode. In single-rail mode, transmit clock and NRZ data are applied to TCLK_n and TPOS_n/TDATA_n pins respectively. In single-rail and Hardware mode the TNEG_n/CODES_n input can be used as the CODES function. With TNEG_n/CODES_n tied "Low", HDB3 or B8ZS encoding and decoding are enabled for E1 and T1 modes respectively. With TNEG_n/CODES_n tied "High", the AMI coding scheme is selected. In both dual or single-rail modes of operations, the transmitter converts digital input data to a bipolar format before being transmitted to the line. TRANSMIT CLOCK (TCLK) SAMPLING EDGE Serial transmit data at TPOS_n/TDATA_n and TNEG_n/CODES_n are clocked into the XRT83L34 under the synchronization of TCLK_n. With a "0" written to the TCLKE interface bit, or by pulling the TCLKE pin "Low", input data is sampled on the falling edge of TCLK_n. The sampling edge is inverted with a "1" written to TCLKE interface bit, or by connecting the TCLKE pin "High". 25 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY FIGURE 12. TRANSMIT CLOCK AND INPUT DATA TIMING TCLKR TCLKF TCLK TPOS/TDATA or TNEG TSU THO TRANSMIT HDB3/B8ZS ENCODER The Encoder function is available in both Hardware and Host modes on a per channel basis by controlling the TNEG_n/CODES_n pin or CODES interface bit. The encoder is only available in single-rail mode. In E1 mode and with HDB3 encoding selected, any sequence with four or more consecutive zeros in the input serial data from TPOS_n/TDATA_n, will be removed and replaced with 000V or B00V, where "B" indicates a pulse conforming with the bipolar rule and "V" representing a pulse violating the rule. An example of HDB3 Encoding is shown in Table 3. In a T1 system, an input data sequence with eight or more consecutive zeros will be removed and replaced using the B8ZS encoding rule. An example of Bipolar with 8 Zero Substitution (B8ZS) encoding scheme is shown in Table 4. Writing a "1" into the CODES_n interface bit or connecting the TNEG_n/ CODES_n pin to a "High" level selects the AMI coding for both E1 or T1 systems. TABLE 3: EXAMPLES OF HDB3 ENCODING NUMBER OF PULSE BEFORE NEXT 4 ZEROS Input HDB3 (case1) HDB3 (case2) odd even NEXT 4 BITS 0000 000V B00V TABLE 4: EXAMPLES OF B8ZS ENCODING CASE 1 Input B8ZS AMI Output + PRECEDING PULSE + NEXT 8 BITS 00000000 000VB0VB 000+ -0- + CASE 2 Input B8ZS AMI Output 00000000 000VB0VB 000- +0+ - 26 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 DRIVER FAILURE MONITOR (DMO) The driver monitor circuit is used to detect transmit driver failure by monitoring the activities at TTIP and TRING outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the transmit input. If the transmitter of a channel has no output for more than 128 clock cycles, the corresponding DMO pin goes "High" and remains "High" until a valid transmit pulse is detected. In Host mode, the failure of the transmit channel is reported in the corresponding interface bit. If the DMOIE bit is also enabled, any transition on the DMO interface bit will generate an interrupt. The driver failure monitor is supported in both Hardware and Host modes on a per channel basis. TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT The transmit pulse shaper circuit uses the high speed clock from the Master timing generator to control the shape and width of the transmitted pulse. The internal high-speed timing generator eliminates the need for a tightly controlled transmit clock (TCLK) duty cycle. With the jitter attenuator not in the transmit path, the transmit output will generate no more than 0.025Unit Interval (UI) peak-to-peak jitter. In Hardware mode, the state of the A[4:0]/EQC[4:0] pins determine the transmit pulse shape for all eight channels. In Host mode transmit pulse shape can be controlled on a per channel basis using the interface bits EQC[4:0]. The chip supports five fixed transmit pulse settings for T1 Short-haul applications plus a fully programmable waveform generator for arbitrary transmit output pulse shapes. Transmit Line Build-Outs for T1 long-haul application are supported from 0dB to -22.5dB in three 7.5dB steps. The choice of the transmit pulse shape and LBO under the control of the interface bits are summarized in Table 5. For CSU LBO transmit pulse design information, refer to ANSI T1.403-1993 Network-to-Customer Installation specification, Annex-E. NOTE: EQC[4:0] determine the T1/E1 operating mode of the XRT83L34. When EQC4 = "1" and EQC3 = "1", the XRT83L34 is in the E1 mode, otherwise it is in the T1/J1 mode. TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS EQC4 0 0 0 0 EQC3 0 0 0 0 EQC2 0 0 0 0 EQC1 0 0 1 1 EQC0 0 1 0 1 E1/T1 MODE & RECEIVE SENSITIVITY T1 Long Haul/36dB T1 Long Haul/36dB T1 Long Haul/36dB T1 Long Haul/36dB TRANSMIT LBO 0dB -7.5dB -15dB -22.5dB CABLE 100/ TP 100/ TP 100/ TP 100/ TP CODING B8ZS B8ZS B8ZS B8ZS 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 T1 Long Haul/45dB T1 Long Haul/45dB T1 Long Haul/45dB T1 Long Haul/45dB 0dB -7.5dB -15dB -22.5dB 100/ TP 100/ TP 100/ TP 100/ TP B8ZS B8ZS B8ZS B8ZS 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 T1 Short Haul/15dB T1 Short Haul/15dB T1 Short Haul/15dB T1 Short Haul/15dB T1 Short Haul/15dB T1 Short Haul/15dB 0-133 ft./ 0.6dB 133-266 ft./ 1.2dB 266-399 ft./ 1.8dB 399-533 ft./ 2.4dB 533-655 ft./ 3.0dB Arbitrary Pulse 100/ TP 100/ TP 100/ TP 100/ TP 100/ TP 100/ TP B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS 27 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS EQC4 EQC3 EQC2 EQC1 EQC0 E1/T1 MODE & RECEIVE SENSITIVITY TRANSMIT LBO CABLE CODING 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB 0-133 ft./ 0.6dB 133-266 ft./ 1.2dB 266-399 ft./ 1.8dB 399-533 ft./ 2.4dB 533-655 ft./ 3.0dB Arbitrary Pulse 100/ TP 100/ TP 100/ TP 100/ TP 100/ TP 100/ TP B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB 0dB -7.5dB -15dB -22.5dB 100/ TP 100/ TP 100/ TP 100/ TP B8ZS B8ZS B8ZS B8ZS 1 1 1 1 0 0 0 0 0 1 E1 Long Haul/36dB E1 Long Haul/36dB ITU G.703 ITU G.703 75 Coax 120 TP HDB3 HDB3 1 1 1 1 0 0 1 1 0 1 E1 Long Haul/43dB E1 Long Haul/43dB ITU G.703 ITU G.703 75 Coax 120 TP HDB3 HDB3 1 1 1 1 1 1 0 0 0 1 E1 Short Haul E1 Short Haul ITU G.703 ITU G.703 75 Coax 120 TP HDB3 HDB3 1 1 1 1 1 1 1 1 0 1 E1 Gain Mode E1 Gain Mode ITU G.703 ITU G.703 75 Coax 120 TP HDB3 HDB3 28 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TRANSMIT AND RECEIVE TERMINATIONS The XRT83L34 is a versatile LIU that can be programmed to use one Bill of Materials (BOM) for worldwide applications for T1, J1 and E1. For specific applications the internal terminations can be disabled to allow the use of existing components and/or designs. RECEIVER (CHANNELS 0 - 3) INTERNAL RECEIVE TERMINATION MODE In Hardware mode, RXTSEL (Pin 83) can be tied "High" to select internal termination mode for all receive channels or tied "Low" to select external termination mode. Individual channel control can only be done in Host mode. By default the XRT83L34 is set for external termination mode at power up or at Hardware reset. TABLE 6: RECEIVE TERMINATION CONTROL RXTSEL 0 1 RX TERMINATION EXTERNAL INTERNAL In Host mode, bit 7 in the appropriate channel register, (Table 20, "Microprocessor Register #1, Bit Description," on page 47), is set "High" to select the internal termination mode for that specific receive channel. FIGURE 13. SIMPLIFIED DIAGRAM FOR THE INTERNAL RECEIVE AND TRANSMIT TERMINATION MODE Channel _n TTIP TPO S TNEG TCLK TX Line Driver R int 1 0.68 F T1 5 TTIP 75 , 100 110 or 120 TRING R int TRING 4 1:2 8 RTIP RPOS RNEG RCLK RX Equalizer R int 5 T2 1 RTIP 75 , 100 110 or 120 RRING 8 1:1 4 RRING If the internal termination mode (RXTSEL = "1") is selected, the effective impedance for E1, T1 or J1 can be achieved either with an internal resistor or a combination of internal and external resistors as shown in Table 7. NOTE: In Hardware mode, pins RXRES[1:0] control all channels. 29 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 7: RECEIVE TERMINATIONS RXTSEL 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TERSEL1 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TERSEL0 x 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RXRES1 x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 RXRES0 x 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Rext Rext Rint MODE T1/E1/J1 T1 J1 E1 E1 T1 J1 E1 E1 T1 J1 E1 E1 T1 J1 E1 E1 100 110 75 120 172 204 108 240 192 232 116 280 300 412 150 600 240 240 240 240 210 210 210 210 150 150 150 150 Figure 14 is a simplified diagram for T1 (100) in the external receive termination mode. Figure 15 is a simplified diagram for E1 (75) in the external receive termination mode. FIGURE 14. SIMPLIFIED DIAGRAM FOR T1 IN THE EXTERNAL TERMINATION MODE (RXTSEL= 0) X R T 8 3 L 3 4 L IU 3 .1 T T IP 3 .1 T R IN G R T IP 100 R R IN G 1 :1 100 100 1 :2 .4 5 30 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 FIGURE 15. SIMPLIFIED DIAGRAM FOR E1 IN EXTERNAL TERMINATION MODE (RXTSEL= 0) X R T 8 3 L 3 4 L IU T T IP 9 .1 1 :2 .4 5 9 .1 T R IN G R T IP 75 R R IN G 1 :1 75 75 TRANSMITTER (CHANNELS 0 - 3) TRANSMIT TERMINATION MODE In Hardware mode, TXTSEL (Pin 84) can be tied "High" to select internal termination mode for all transmit channels or tied "Low" for external termination. Individual channel control can be done only in Host mode. In Host mode, bit 6 in the appropriate register for a given channel is set "High" to select the internal termination mode for that specific transmit channel, see Table 20, "Microprocessor Register #1, Bit Description," on page 47. TABLE 8: TRANSMIT TERMINATION CONTROL TXTSEL 0 1 TX TERMINATION EXTERNAL INTERNAL TX TRANSFORMER RATIO 1:2.45 1:2 For internal termination, the transformer turns ratio is always 1:2. In internal mode, no external resistors are used. An external capacitor of 0.68F is used for proper operation of the internal termination circuitry, see Figure 13. TABLE 9: TERMINATION SELECT CONTROL TERSEL1 0 0 1 1 TERSEL0 0 1 0 1 TERMINATION 100 110 75 120 EXTERNAL TRANSMIT TERMINATION MODE By default the XRT83L34 is set for external termination mode at power up or at Hardware reset. When external transmit termination mode is selected, the internal termination circuitry is disabled. The value of the external resistors is chosen for a specific application according to the turns ratio selected by TRATIO (Pin 127) in Hardware mode or bit 0 in the appropriate register for a specific channel in Host mode, see Table 10 and Table 22, "Microprocessor Register #3, Bit Description," on page 51. Figure 14 is a simplified block 31 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY diagram for T1 (100) in the external termination mode. Figure 15 is a simplified block diagram for E1 (75) in the external termination mode. TABLE 10: TRANSMIT TERMINATION CONTROL TRATIO 0 1 TURNS RATIO 1:2 1:2.45 Table 11 summarizes the transmit terminations. TABLE 11: TRANSMIT TERMINATIONS TERSEL1 TERSEL0 TXTSEL 0=EXTERNAL 1=INTERNAL TRATIO Rint SET BY CONTROL BITS n Rext Cext n, Rext, AND Cext ARE SUGGESTED SETTINGS 0 T1 100 0 0 0 0 0 0 0 1 0 1 x 0 0 12.5 2.45 2 2 3.1 3.1 0 0 0 0.68F 0 J1 110 0 0 1 1 1 0 0 1 0 1 x 0 0 13.75 2.45 2 2 3.1 3.1 0 0 0 0.68F 1 E1 75 1 1 0 0 0 0 0 1 0 1 x 0 0 9.4 2.45 2 2 6.2 9.1 0 0 0 0.68F 1 E1 120 1 1 1 1 1 0 0 1 0 1 x 0 0 15 2.45 2 2 6.2 9.1 0 0 0 0.68F REDUNDANCY APPLICATIONS Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without losing data. System designers can achieve this by implementing common redundancy schemes with the XRT83L34 Line Interface Unit (LIU). The XRT83L34 offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. These features allow system designers to implement redundancy applications that ensure reliability. The Internal Impedance mode eliminates the need for external relays when using the 1:1 and 1+1 redundancy schemes. 32 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PROGRAMMING CONSIDERATIONS In many applications switching the control of the transmitter outputs and the receiver line impedance to hardware control will provide faster transmitter ON/OFF switching. In Host Mode, there are two bits in register 130 (82H) that control the transmitter outputs and the Rx line impedance select, TXONCNTL (Bit 7) and TERCNTL (Bit 6). Setting bit-7 (TXONCNTL) to a "1" transfers the control of the Transmit On/Off function to the TXON_n Hardware control pins. (Pins 90 through 93 and pins 169 through 172). Setting bit-6 (TERCNTL) to a "1" transfers the control of the Rx line impedance select (RXTSEL) to the RXTSEL Hardware control pin (pin 83). Either mode works well with redundancy applications. The user can determine which mode has the fastest switching time for a unique application. TYPICAL REDUNDANCY SCHEMES s s s *1:1 One backup card for every primary card (Facility Protection) *1+1 One backup card for every primary card (Line Protection) *N+1One backup card for N primary cards 1:1 REDUNDANCY A 1:1 facility protection redundancy scheme has one backup card for every primary card. When using 1:1 redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This eliminates the need for external relays and provides one bill of materials for all interface modes of operation. The transmit and receive sections of the LIU device are described separately. 1+1 REDUNDANCY A 1+1 line protection redundancy scheme has one backup card for every primary card, and the receivers on the backup card are monitoring the receiver inputs. Therefore, the receivers on both cards need to be active. The transmit outputs require no external resistors. The transmit and receive sections of the LIU device are described separately. TRANSMIT 1:1 & 1+1 REDUNDANCY For 1:1 and 1+1 redundancy, the transmitters on the primary and backup card should be programmed for Internal Impedance mode. The transmitters on the backup card should be tri-stated. Select the appropriate impedance for the desired mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for blocking DC bias. See Figure 16 for a simplified block diagram of the transmit section for 1:1 and 1+1 redundancy scheme. NOTE: For simplification, the over voltage protection circuitry was omitted. 33 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY FIGURE 16. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT SECTION FOR 1:1 & 1+1 REDUNDANCY B ackplane Interface Line Interface C ard P rim ary C ard X R T 83L34 1:2 or 1:2.45 Tx 0.68 F T 1/E 1 Line T xT S E L=1, Internal B ackup C ard X R T 83L34 Tx T xT S E L=1, Internal 0.68 F RECEIVE 1:1 & 1+1 REDUNDANCY For 1:1 and 1+1 redundancy, the receivers on the primary card should be programmed for Internal Impedance mode. The receivers on the backup card should be programmed for External Impedance mode. Since there is no external resistor in the circuit, the receivers on the backup card will be high impedance. This key design feature eliminates the need for relays and provides one bill of materials for all interface modes of operation. Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to Internal Impedance mode, then the primary card to External Impedance mode. See Figure 17 for a simplified block diagram of the receive section for a 1:1 and 1+1 redundancy scheme. NOTE: For simplification, the over voltage protection circuitry was omitted. FIGURE 17. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR 1:1 AND 1+1 REDUNDANCY B ackplane Interface Line Interface C ard P rim ary C ard X R T 83L34 1:1 Rx T 1/E 1 Line R xT S E L=1, Internal B ackup C ard X R T 83L34 Rx R xT S E L=0, E xternal 34 PRELIMINARY N+1 REDUNDANCY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention, external relays are necessary when using this redundancy scheme. The advantage of relays is that they create complete isolation between the primary cards and the backup card. This allows all transmitters and receivers on the primary cards to be configured in internal impedance mode, providing one bill of materials for all interface modes of operation. The transmit and receive sections of the XRT83L34 are described separately. TRANSMIT For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance mode providing one bill of materials for T1/E1/J1. The transmitters on the backup card do not have to be tri-stated. To swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A 0.68F capacitor is used in series with TTIP for blocking DC bias. See Figure 18 for a simplified block diagram of the transmit section for an N+1 redundancy scheme. NOTE: For simplification, the over voltage protection circuitry was omitted. FIGURE 18. SIMPLIFIED BLOCK DIAGRAM - TRANSMIT SECTION FOR N+1 REDUNDANCY B a ckp lan e In terfa ce Lin e In te rfac e C ard P rim a ry C a rd X R T 83 L 4 1:2 or 1 :2.45 Tx 0 .68 F T 1/E 1 Lin e TxTS E L=1 , Internal P rim ary C a rd X R T 83 L3 4 1:2 or 1 :2.45 Tx 0.6 8 F T 1 /E 1 L ine TxTS E L=1 , Internal P rim a ry C a rd X R T 83 L 34 1:2 or 1 :2.45 Tx 0 .68 F T 1 /E 1 L ine TxTS E L=1 , Internal B a cku p C a rd X R T 83 L 34 Tx T xTS EL=1, Inte rnal 0 .68 F 35 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY RECEIVE For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance mode. The receivers on the backup card should be programmed for external impedance mode. Since there is no external resistor in the circuit, the receivers on the backup card will be high impedance. Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to internal impedance mode, then the primary card to external impedance mode. See Figure 19. for a simplified block diagram of the receive section for a N+1 redundancy scheme. NOTE: For simplification, the over voltage protection circuitry was omitted. FIGURE 19. SIMPLIFIED BLOCK DIAGRAM - RECEIVE SECTION FOR N+1 REDUNDANCY B ackp lane Interface Line Interface C ard P rim ary C ard X R T 83L34 1:1 Rx T 1/E 1 Line R xT SEL=1, Internal P rim ary C ard X R T 83L34 1:1 Rx T 1/E 1 Line R xT SEL=1, Internal P rim ary C ard X R T 83L34 1:1 Rx T 1/E 1 Line R xT SEL=1, Internal B a ckup C ard X R T 83L34 Rx R xT SEL=1, External 36 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PATTERN TRANSMIT AND DETECT FUNCTION Several test and diagnostic patterns can be generated and detected by the chip. In Hardware mode each channel can be independently programmed to transmit an All Ones pattern by applying a "High" level to the corresponding TAOS_n pin. In Host mode, the three interface bits TXTEST[2:0] control the pattern generation and detection independently for each channel according to Table 12. TABLE 12: PATTERN TRANSMISSION CONTROL TXTEST2 0 1 1 1 1 TXTEST1 x 0 0 1 1 TXTEST0 x 0 1 0 1 TEST PATTERN None TDQRSS TAOS TLUC TLDC TRANSMIT ALL ONES (TAOS) This feature is available in both Hardware and Host modes. With the TAOS_n pin connected to a "High" level or when interface bits TXTEST2="1", TXTEST1="0" and TXTEST0="1" the transmitter ignores input from TPOS_n/TDATA_n and TNEG_n/CODES_n pins and sends a continuous AMI encoded all "Ones" signal to the line, using TCLK_n clock as the reference. In addition, when the Hardware pin and interface bit ATAOS is activated, the chip will automatically transmit the All "Ones" data from any channel that detects an RLOS condition. This feature is not available on a per channel basis. TCLK_n must NOT be tied "Low". NETWORK LOOP CODE DETECTION AND TRANSMISSION This feature is available in Host mode only. When the interface bits TXTEST2="1", TXTEST1="1" and TXTEST0="0" the chip is enabled to transmit the "00001" Network Loop-Up Code from the selected channel requesting a Loop-Back condition from the remote terminal. Simultaneously setting the interface bits NLCDE1="0" and NLCDE0="1" enables the Network Loop-Up code detection in the receiver. If the "00001" Network Loop-Up code is detected in the receive data for longer than 5 seconds, the NLCD bit in the interface register is set indicating that the remote terminal has activated remote Loop-Back and the chip is receiving its own transmitted data. When the interface bits TXTEST2="1", TXTEST1="1" and TXTEST0="1" the chip is enabled to transmit the Network Loop-Down Code (TLDC) "001" from the selected channel requesting the remote terminal the removal of the Loop-Back condition. In the Host mode each channel is capable of monitoring the contents of the receive data for the presence of Loop-Up or Loop-Down code from the remote terminal. In the Host mode the two interface bits NLCDE[1:0] control the Loop-Code detection independently for each channel according to Table 13. TABLE 13: LOOP-CODE DETECTION CONTROL NLCDE1 0 0 1 1 NLCDE0 0 1 0 1 Disable Loop-Code Detection Detect Loop-Up Code in Receive Data Detect Loop-Down Code in Receive Data Automatic Loop-Code detection and Remote Loop-Back Activation CONDITION Setting the interface bits to NLCDE1="0" and NLCDE0="1" activates the detection of the Loop-Up code in the receive data. If the "00001" Network Loop-Up code is detected in the receive data for longer than 5 seconds, the NLCD interface bit is set to "1" and stays in this state for as long as the receiver continues to receive the 37 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY Network Loop-Up Code. In this mode if the NLCD interrupt is enabled, the chip will initiate an interrupt on every transition of NLCD. The host has the option to ignore the request from the remote terminal, or to respond to the request and manually activate Remote Loop-Back. The host can subsequently activate the detection of the Loop-Down Code by setting NLCDE1="1" and NLCDE0="0". In this case, receiving the "001" Loop-Down Code for longer than 5 seconds will set the NLCD bit to "1" and if the NLCD interrupt is enabled, the chip will initiate an interrupt on every transition of NLCD. The host can respond to the request from the remote terminal and remove Loop-Back condition. In the manual Network Loop-Up (NLCDE1="0" and NLCDE0="1") and LoopDown (NLCDE1="1" and NLCDE0="0") Code detection modes, the NLCD interface bit will be set to "1" upon receiving the corresponding code in excess of 5 seconds in the receive data. The chip will initiate an interrupt any time the status of the NLCD bit changes and the Network Loop-code interrupt is enabled. In the Host mode, setting the interface bits NLCDE1="1" and NLCDE0="1" enables the automatic Loop-Code detection and Remote Loop-Back activation mode if, TXTEST[2:0] is NOT equal to "110". As this mode is initiated, the state of the NLCD interface bit is reset to "0" and the chip is programmed to monitor the receive input data for the Loop-Up Code. If the "00001" Network Loop-Up Code is detected in the receive data for longer than 5 seconds in addition to the NLCD bit in the interface register being set, Remote Loop-Back is automatically activated. The chip stays in remote Loop-Back even if it stops receiving the "00001" pattern. After the chip detects the Loop-Up code, sets the NLCD bit and enters Remote Loop-Back, it automatically starts monitoring the receive data for the Loop-Down code. In this mode however, the NLCD bit stays set even if the receiver stops receiving the Loop-Up code, which is an indication to the host that the Remote Loop-Back is still in effect. Remote Loop-Back is removed if the chip detects the "001" Loop-Down code for longer than 5 seconds. Detecting the "001" code also results in resetting the NLCD interface bit and initiating an interrupt. The Remote Loop-Back can also be removed by taking the chip out of the Automatic detection mode by programming it to operate in a different state. The chip will not respond to remote Loop-Back request if Local Analog Loop-Back is activated locally. When programmed in Automatic detection mode the NLCD interface bit stays "High" for the whole time the Remote Loop-Back is activated and initiates an interrupt any time the status of the NLCD bit changes provided the Network Loop-code interrupt is enabled. TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) Each channel of XRT83L34 includes a QRSS pattern generation and detection block for diagnostic purposes that can be activated only in the Host mode by setting the interface bits TXTEST2="1", TXTEST1="0" and TXTEST0="0". For T1 systems, the QRSS pattern is a 220-1pseudo-random bit sequence (PRBS) with no more than 14 consecutive zeros. For E1 systems, the QRSS pattern is 215 -1 PRBS with an inverted output. With QRSS and Analog Local Loop-Back enabled simultaneously, and by monitoring the status of the QRPD interface bit, all main functional blocks within the transceiver can be verified. When the receiver achieves QRSS synchronization with fewer than 4 errors in a 128 bits window, QRPD changes from "Low" to "High". After pattern synchronization, any bit error will cause QRPD to go "Low" for one clock cycle. If the QRPDIE bit is enabled, any transition on the QRPD bit will generate an interrupt. With TDQRSS activated, a bit error can be inserted in the transmitted QRSS pattern by transitioning the INSBER interface bit from "0" to "1". Bipolar violation can also be inserted either in the QRSS pattern, or input data when operating in the single-rail mode by transitioning the INSBPV interface bit from "0" to "1". The state of INSBER and INSBPV bits are sampled on the rising edge of the TCLK_n. To insure the insertion of the bit error or bipolar violation, a "0" should be written in these bit locations before writing a "1". 38 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 LOOP-BACK MODES The XRT83L34 supports several Loop-Back modes under both Hardware and Host control. In Hardware mode the two LOOP[1:0] pins control the Loop-Back functions for each channel independently according to Table 14. TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE LOOP1 0 0 1 1 LOOP0 0 1 0 1 LOOP-BACK MODE None Analog Remote Digital In Host mode the Loop-Back functions are controlled by the three LOOP[2:0] interface bits. Each channel can be programmed independently according to Table 15. TABLE 15: LOOP-BACK CONTROL IN HOST MODE LOOP2 0 1 1 1 1 LOOP1 X 0 0 1 1 LOOP0 X 0 1 0 1 LOOP-BACK MODE None Dual Analog Remote Digital LOCAL ANALOG LOOP-BACK (ALOOP) With Local Analog Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog input of the receiver. External inputs at RTIP/RRING in this mode are ignored while valid transmit data continues to be sent to the line. Local Analog Loop-Back exercises most of the functional blocks of the XRT83L34 including the jitter attenuator which can be selected in either the transmit or receive paths. Local Analog Loop-Back is shown in Figure 20. FIGURE 20. LOCAL ANALOG LOOP-BACK SIGNAL FLOW TPOS TNEG TCLK Encoder JA Timing Control TTIP Tx TRING RCLK RPOS RNEG Decoder Data & Clock Recovery Rx RTIP RRING In this mode, the jitter attenuator (if selected) can be placed in the transmit or receive path. 39 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY REMOTE LOOP-BACK (RLOOP) With Remote Loop-Back activated, receive data after the jitter attenuator (if selected in the receive path) is looped back to the transmit path using RCLK as transmit timing. In this mode transmit clock and data are ignored, while RCLK and receive data will continue to be available at their respective output pins. Remote Loop-Back with jitter attenuator selected in the receive path is shown in Figure 21. FIGURE 21. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH TPOS TNEG TCLK Encoder Timing Control TTIP Tx TRING RCLK RPOS RNEG Decoder JA Data & Clock Recovery RTIP Rx RRING In the Remote Loop-Back mode if the jitter attenuator is selected in the transmit path, the receive data from the Clock and Data Recovery block is looped back to the transmit path and is applied to the jitter attenuator using RCLK as transmit timing. In this mode the transmit clock and data are also ignored, while RCLK and received data will continue to be available at their respective output pins. Remote Loop-Back with the jitter attenuator selected in the transmit path is shown in Figure 22. FIGURE 22. REMOTE LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH TPOS TNEG TCLK Encoder JA Timing Control Tx TTIP TRING RCLK RPOS RNEG Decoder Clock & Data Recovery RTIP Rx RRING 40 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 DIGITAL LOOP-BACK (DLOOP) Digital Loop-Back or Local Loop-Back allows the transmit clock and data to be looped back to the corresponding receiver output pins through the encoder/decoder and jitter attenuator. In this mode, receive data and clock are ignored, but the transmit data will be sent to the line uninterrupted. This loop back feature allows users to configure the line interface as a pure jitter attenuator. The Digital Loop-Back signal flow is shown in Figure 23. FIGURE 23. DIGITAL LOOP-BACK MODE WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH TPOS TNEG TCLK Encoder JA Timing Control TTIP Tx TRING RCLK RPOS RNEG Decoder Data & Clock Recovery RTIP Rx RRING DUAL LOOP-BACK Figure 24 depicts the data flow in dual-loopback. In this mode, selecting the jitter attenuator in the transmit path will have the same result as placing the jitter attenuator in the receive path. In dual Loop-Back mode the recovered clock and data from the line are looped back through the transmitter to the TTIP and TRING without passing through the jitter attenuator. The transmit clock and data are looped back through the jitter attenuator to the RCLK and RPOS/RDATA and RNEG pins. FIGURE 24. SIGNAL FLOW IN DUAL LOOP-BACK MODE TPOS TNEG TCLK JA Encoder Timing Control Tx TTIP TRING RCLK RPOS RNEG Decoder Data & Clock Recovery RTIP Rx RRING 41 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY MICROPROCESSOR PARALLEL INTERFACE XRT83L34 is equipped with a microprocessor interface for easy device configuration. The parallel port of the XRT83L34 is compatible with both Intel and Motorola address and data buses. The XRT83L34 has an 8-bit address A[7:0] input and 8-bit bi-directional data bus D[7:0]. The signals required for a generic microprocessor to access the internal registers are described in Table 16. TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION D[7:0] A[7:0] PTS1 PTS2 Data Input (Output): 8 bits bi-directional Read/Write data bus for register access. Address Input: 8 bit address to select internal register location. Microprocessor Type Select: PTS2 PTS1 P T yp e 0 0 1 1 0 1 0 1 68H C 11, 8051, 80C 188 (async.) M otorola 68K (async.) Inte l x86 (sync.) Inte l i960, M otorola 860 (sync.) PCLK Microprocessor Clock Input: Input clock for synchronous microprocessor operation. Maximum clock speed is 54MHz. This pin is internally pulled "Low" for asynchronous microprocessor operation when no clock is present. Address Latch Input (Address Strobe): -Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE. -Motorola bus timing, the address inputs are latched into the internal register on the falling edge of AS. Chip Select Input: This signal must be "Low" in order to access the parallel port. Read Input (Data Strobe): -Intel bus timing, a "Low" pulse on RD selects a read operation when CS pin is "Low". -Motorola bus timing, a "Low" pulse on DS indicates a read or write operation when CS pin is "Low". Write Input (Read/Write): -Intel bus timing, a "Low" pulse on WR selects a write operation when CS pin is "Low". -Motorola bus timing, a "High" pulse on R/W selects a read operation and a "Low" pulse on R/W selects a write operation when CS pin is "Low". Ready Output (Data Transfer Acknowledge Output): -Intel bus timing, RDY is asserted "High" to indicate the XRT83L34 has completed a read or write operation. -Motorola bus timing, DTACK is asserted "Low" to indicate the XRT83L34 has completed a read or write operation. Interrupt Output: This pin is asserted "Low" to indicate an interrupt caused by an alarm condition in the device status registers. The activation of this pin can be blocked by setting the GIE bit to "0" in the Command Control register. ALE_AS CS RD_DS WR_R/W RDY_DTACK INT 42 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 MICROPROCESSOR REGISTER TABLES The microprocessor interface consists of 256 addressable locations. Each channel uses 16 dedicated 7 bit registers for independent programming and control. There are four additional registers for global control of all channels and two registers for device identification and revision numbers. The remaining registers are for factory test and future expansion. The control register map and the function of the individual bits are summarized in Table 17 and Table 18 respectively. TABLE 17: MICROPROCESSOR REGISTER ADDRESS REGISTER ADDRESS REGISTER NUMBER HEX 0 - 15 16 - 31 32 - 47 48 - 63 64 - 67 68 - 75 76-125 126 127 0x00 - 0x0F 0x10 -0x1F 0x20 - 0x2F 0x30 - 0x3F 0x40 - 0x43 0x44 - 0x4B 0x4C - 0x7D 0x7E 0x7F BINARY 0000000 - 0001111 0010000 - 0011111 0100000 - 0101111 0110000 - 0111111 1000000 - 1000011 1000100 - 1001011 1001100 - 1111101 1111110 1111111 Channel 0 Control Registers Channel 1 Control Registers Channel 2 Control Registers Channel 3 Control Registers Command Control Registers for All 4 Channels R/W registers reserved for testing purpose. Reserved Device ID Device Revision ID FUNCTION TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION REG. # ADDRESS REG. TYPE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Channel 0 Control Registers 0 0000000 Hex 0x00 0000001 Hex 0x01 0000010 Hex 0x02 0000011 Hex 0x03 0000100 Hex 0x04 0000101 Hex 0x05 0000110 Hex 0x06 0000111 Hex 0x07 0001000 Hex 0x08 R/W Reserved Reserved RXON_n EQC4_n EQC3_n EQC2_n EQC1_n EQC0_n 1 R/W RXTSEL_n TXTSEL_n TERSEL1_n TERSEL0_n JASEL1_n JASEL0_n JABW_n FIFOS_n 2 R/W INVQRSS_n TXTEST2_n TXTEST1_n TXTEST0_n TXON_n LOOP2_n LOOP1_n LOOP0_n 3 R/W NLCDE1_n NLCDE0_n CODES_n RXRES1_n RXRES0_n INSBPV_n INSBER_n TRATIO_n 4 R/W Reserved DMOIE_n FLSIE_n LCVIE_n NLCDIE_n AISDIE_n RLOSIE_n QRPDIE_n 5 RO Reserved DMO_n FLS_n LCV_n NLCD_n AISD_n RLOS_n QRPD_n 6 RUR Reserved DMOIS_n FLSIS_n LCVIS_n NLCDIS_n AISDIS_n RLOSIS_n QRPDIS_n 7 RO Reserved Reserved CLOS5_n CLOS4_n CLOS3_n CLOS2_n CLOS1_n CLOS0_n 8 R/W X B6S1_n B5S1_n B4S1_n B3S1_n B2S1_n B1S1_n B0S1_n 43 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY BIT 1 B1S2_n BIT 0 B0S2_n TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION REG. # 9 ADDRESS 0001001 Hex 0x09 0001010 Hex 0x0A 0001011 Hex 0x0B 0001100 Hex 0x0C 0001101 Hex 0x0D 0001110 Hex 0x0E 0001111 Hex 0x0F REG. TYPE R/W BIT 7 X BIT 6 B6S2_n BIT 5 B5S2_n BIT 4 B4S2_n BIT 3 B3S2_n BIT 2 B2S2_n 10 R/W X B6S3_n B5S3_n B4S3_n B3S3_n B2S3_n B1S3_n B0S3_n 11 R/W X B6S4_n B5S4_n B4S4_n B3S4_n B2S4_n B1S4_n B0S4_n 12 R/W X B6S5_n B5S5_n B4S5_n B3S5_n B2S5_n B1S5_n B0S5_n 13 R/W X B6S6_n B5S6_n B4S6_n B3S6_n B2S6_n B1S6_n B0S6_n 14 R/W X B6S7_n B5S7_n B4S7_n B3S7_n B2S7_n B1S7_n B0S7_n 15 R/W X B6S8_n B5S8_n B4S8_n B3S8_n B2S8_n B1S8_n B0S8_n Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Reset = 0 Command Control Global Registers for all 8 channels 16-31 001xxxx Hex 0x100x1F 010xxxx Hex 0x20ox2F 011xxxx Hex 0x300x3F R/W Channel 1Control Register (see Registers 0-15 for description) 32-47 R/W Channel 2 Control Register (see Registers 0-15 for description) 48-63 R/W Channel 3 Control Register (see Registers 0-15 for description) Command Control Global Registers 64 1000000 Hex 0x40 1000001 Hex 0x41 1000010 Hex 0x42 1000011 Hex 0x43 R/W SR/DR ATAOS RCLKE TCLKE DATAP Reserved GIE SRESET 65 R/W E1arben CLKSEL2 CLKSEL1 CLKSEL0 MCLKRATE RXMUTE EXLOS ICT 66 R/W GAUGE1 Gauge2 TXONCNTL TERCNTL SL_1 SL_0 EQG_1 EQG_0 67 R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Test Registers for channels 0 - 3 68 1000100 Hex 0x44 1000101 Hex 0x45 1000110 Hex 0x46 1000111 Hex 0x47 1001000 Hex 0x48 1001001 Hex 0x49 R/W Test byte 0 69 R/W Test byte 1 70 R/W Test byte 2 71 R/W Test byte 3 72 R/W Test byte 4 73 R/W Test byte 5 44 PRELIMINARY REG. # 74 ADDRESS 1001010 Hex 0x4A 1001011 Hex 0x4B REG. TYPE XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R/W Test byte 6 75 R/W Test byte 7 Unused Registers 76 1001100 Hex 0x4C .... 125 1111101 Hex 0x7D ID Registers 126 1111110 Hex 0x7E 1111111 Hex 0x7F DEVICE ID: HEX = FB, Binary = 1111011 127 DEVICE Revision ID 45 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY MICROPROCESSOR REGISTER DESCRIPTIONS TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION REGISTER ADDRESS 0000000 0010000 0100000 0110000 BIT # D7 D6 D5 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved Reserved RXON_n Receiver ON: Writing a "1" into this bit location turns on the Receive Section of channel n. Writing a "0" shuts off the Receiver Section of channel n. R/W R/W R/W 0 0 FUNCTION REGISTER TYPE RESET VALUE NOTES: 1. This bit provides independent turn-off or turn-on control of each receiver channel. 2. In Hardware mode all receiver channels are always on. D4 EQC4_n Equalizer Control bit 4: This bit together with EQC[3:0] are used for controlling transmit pulse shaping, transmit line buildout (LBO) and receive monitoring for either T1 or E1 Modes of operation. See Table 5 for description of Equalizer Control bits. D3 D2 D1 D0 EQC3_n EQC2_n EQC1_n EQC0_n Equalizer Control bit 3: See bit D4 description for function of this bit Equalizer Control bit 2: See bit D4 description for function of this bit Equalizer Control bit 1: See bit D4 description for function of this bit Equalizer Control bit 0: See bit D4 description for function of this bit R/W R/W R/W R/W 0 0 0 0 R/W 0 46 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION REGISTER ADDRESS 0000001 0010001 0100001 0110001 BIT # D7 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME RXTSEL_n Receiver Termination Select: In Host mode, this bit is used to select between the internal and external line termination modes for the receiver according to the following table; RXTSEL 0 1 RX Termination External Internal FUNCTION REGISTER TYPE RESET VALUE R/W 0 D6 TXTSEL_n Transmit Termination Select: In Host mode, this bit is used to select between the internal and external line termination modes for the transmitter according to the following table; TXTSEL 0 1 TX Termination External Internal R/W 0 D5 TERSEL1_n Termination Impedance Select1: In Host mode and in internal termination mode, (TXTSEL = "1" and RXTSEL = "1") TERSEL[1:0] control the transmit and receive termination impedance according to the following table; R/W 0 TERSEL1 TERSEL0 0 0 1 1 0 1 0 1 Termination 100 110 75 120 In the internal termination mode, the receiver termination of each receiver is realized completely by internal resistors or by the combination of internal and one fixed external resistor. In the internal termination mode, the transmitter output should be AC coupled to the transformer. D4 TERSEL0_n Termination Impedance Select bit 0: See description of bit D5 for the function of this bit. R/W 0 47 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY R/W 0 TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION D3 JASEL1_n Jitter Attenuator select bit 1: The JASEL1 and JASEL0 bits are used to disable or place the jitter attenuator of each channel independently in the transmit or receive path. JASEL1 bit D3 0 0 1 1 D2 D1 JASEL0_n JABW_n JASEL0 bit D2 0 1 0 1 JA Path JA Disabled JA in Transmit Path JA in Receive Path JA in Receive Path R/W R/W 0 0 Jitter Attenuator select bit 0: See description of bit D3 for the function of this bit. Jitter Attenuator Bandwidth Select: In E1 mode, set this bit to "1" to select a 1.5Hz Bandwidth for the Jitter Attenuator. The FIFO length will be automatically set to 64 bits. Set this bit to "0" to select 10Hz Bandwidth for the Jitter Attenuator in E1 mode. In T1 mode the Jitter Attenuator Bandwidth is permanently set to 3Hz, and the state of this bit has no effect on the Bandwidth. Mode T1 T1 T1 T1 E1 E1 E1 E1 JABW bit D1 0 0 1 1 0 0 1 1 FIFOS_n bit D0 0 1 0 1 0 1 0 1 JA B-W Hz 3 3 3 3 10 10 1.5 1.5 FIFO Size 32 64 32 64 32 64 64 64 D0 FIFOS_n FIFO Size Select: See table of bit D1 above for the function of this bit. R/W 0 48 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION REGISTER ADDRESS 0000010 0010010 0100010 0110010 BIT # D7 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME INVQRSS_n Invert QRSS Pattern: When TQRSS is active, Writing a "1" to this bit inverts the polarity of transmitted QRSS pattern. Writing a "0" sends the QRSS pattern with no inversion. TXTEST2_n Transmit Test Pattern bit 2: This bit together with TXTEST1 and TXTEST0 are used to generate and transmit test patterns according to the following table: TXTEST2 0 1 1 1 1 TXTEST1 X 0 0 1 1 TXTEST0 X 0 1 0 1 Test Pattern No Pattern TDQRSS TAOS TLUC TLDC R/W 0 FUNCTION REGISTER TYPE RESET VALUE D6 R/W 0 TDQRSS (Transmit/Detect Quasi-Random Signal): This condition when activated enables Quasi-Random Signal Source generation and detection for the selected channel number n. In a T1 system QRSS pattern is a 220-1 pseudorandom bit sequence (PRBS) with no more than 14 consecutive zeros. In a E1 system, QRSS is a 215-1 PRBS pattern. TAOS (Transmit All Ones): Activating this condition enables the transmission of an All Ones Pattern from the selected channel number n. TLUC (Transmit Network Loop-Up Code): Activating this condition enables the Network Loop-Up Code of "00001" to be transmitted to the line for the selected channel number n. When Network Loop-Up code is being transmitted, the XRT83L34 will ignore the Automatic Loop-Code detection and Remote Loop-Back activation (NLCDE1 ="1", NLCDE0 ="1", if activated) in order to avoid activating Remote Digital LoopBack automatically when the remote terminal responds to the Loop-Back request. TLDC (Transmit Network Loop-Down Code): Activating this condition enables the network Loop-Down Code of "001" to be transmitted to the line for the selected channel number n. D5 D4 TXTEST1_n Transmit Test pattern bit 1: See description of bit D6 for the function of this bit. TXTEST0_n Transmit Test Pattern bit 0: See description of bit D6 for the function of this bit. R/W R/W 0 0 49 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY R/W 0 TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION D3 TXON_n Transmitter ON: Writing a "1" into this bit location turns on the Transmit Section of channel n. Writing a "0" shuts off the Transmit Section of channel n. In this mode, TTIP_n and TRING_n driver outputs will be tri-stated for power reduction or redundancy applications. NOTE: This bit provides independent turn-off or turn-on control for each transmitter channel. D2 LOOP2_n Loop-Back control bit 2: This bit together with the LOOP1 and LOOP0 bits control the Loop-Back modes of the chip according to the following table: LOOP2 0 1 1 1 1 LOOP1 X 0 0 1 1 LOOP0 X 0 1 0 1 Loop-Back Mode No Loop-Back Dual Loop-Back Analog Loop-Back Remote Loop-Back Digital Loop-Back D1 D0 LOOP1_n LOOP0_n Loop-Back control bit 1: See description of bit D2 for the function of this bit. Loop-Back control bit 0: See description of bit D2 for the function of this bit. R/W R/W 0 0 50 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION REGISTER ADDRESS 0000011 0010011 0100011 0110011 BIT # D7 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME NLCDE1_n Network Loop Code Detection Enable Bit 1: This bit together with NLCDE0_n control the Loop-Code detection of each channel. R/W 0 FUNCTION REGISTER TYPE RESET VALUE NLCDE1 0 0 1 1 NLCDE0 0 1 0 1 Function Disable Loop-code detection Detect Loop-Up code in receive data Detect Loop-Down code in receive data Automatic Loop-Code detection When NLCDE1 ="0" and NLCDE0 = "1" or NLCDE1 = "1" and NLCDE0 = "0", the chip is manually programmed to monitor the receive data for the Loop-Up or Loop-Down code respectively.When the presence of the "00001" or "001" pattern is detected for more than 5 seconds, the status of the NLCD bit is set to "1" and if the NLCD interrupt is enabled, an interrupt is initiated.The Host has the option to control the Loop-Back function manually. Setting the NLCDE1 = "1" and NLCDE0 = "1" enables the Automatic Loop-Code detection and Remote Loop-Back activation mode. As this mode is initiated, the state of the NLCD interface bit is reset to "0" and the chip is programmed to monitor the receive data for the Loop-Up code. If the "00001" pattern is detected for longer than 5 seconds, the NLCD bit is set "1", Remote Loop-Back is activated and the chip is automatically programmed to monitor the receive data for the LoopDown code. The NLCD bit stays set even after the chip stops receiving the Loop-Up code. The Remote Loop-Back condition is removed when the chip receives the Loop-Down code for more than 5 seconds or if the Automatic Loop-Code detection mode is terminated. D6 NLCDE0_n Network Loop Code Detection Enable Bit 0: See description of D7 for function of this bit. Encoding and Decoding Select: Writing a "0" to this bits selects HDB3 or B8ZS encoding and decoding for channel number n. Writing "1" selects an AMI coding scheme. This bit is only active when single rail mode is selected. R/W 0 D5 CODES_n R/W 0 51 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY R/W 0 TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION D4 RXRES1_n Receive External Resistor Control Pin 1: In Host mode, this bit along with the RXRES0_n bit selects the value of the external Receive fixed resistor according to the following table; RXRE S1_n RXRE S0_n R equired Fixed External RX Resistor N o external Fixed R esistor 0 0 1 1 0 1 0 1 240 210 150 D3 D2 RXRES0_n INSBPV_n Receive External Resistor Control Pin 0: For function of this bit see description of D4 the RXRES1_n bit. Insert Bipolar Violation: When this bit transitions from "0" to "1", a bipolar violation is inserted in the transmitted data stream of the selected channel number n. Bipolar violation can be inserted either in the QRSS pattern, or input data when operating in single-rail mode. The state of this bit is sampled on the rising edge of the respective TCLK_n. R/W R/W 0 0 NOTE: To ensure the insertion of a bipolar violation, a "0" should be written in this bit location before writing a "1". D1 INSBER_n Insert Bit Error: With TDQRSS enabled, when this bit transitions from "0" to "1", a bit error will be inserted in the transmitted QRSS pattern of the selected channel number n. The state of this bit is sampled on the rising edge of the respective TCLK_n. R/W 0 NOTE: To ensure the insertion of bit error, a "0" should be written in this bit location before writing a "1". D0 TRATIO_n Transformer Ratio Select: In the external termination mode, writing a "1" to this bit selects a transformer ratio of 1:2 for the transmitter. Writing a "0" sets the transmitter transformer ratio to 1:2.45. In the internal termination mode the transmitter transformer ratio is permanently set to 1:2 and the state of this bit has no effect. R/W 0 52 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION REGISTER ADDRESS 0000100 0010100 0100100 0110100 BIT # D7 D6 D5 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved DMOIE_n FLSIE_n DMO Interrupt Enable: Writing a "1" to this bit enables DMO interrupt generation, writing a "0" masks it. FIFO Limit Status Interrupt Enable: Writing a "1" to this bit enables interrupt generation when the FIFO limit is within to 3 bits, writing a "0" to masks it. Line Code Violation Interrupt Enable: Writing a "1" to this bit enables Line Code Violation interrupt generation, writing a "0" masks it. Network Loop-Code Detection Interrupt Enable: Writing a "1" to this bit enables Network Loop-code detection interrupt generation, writing a "0" masks it. AIS Interrupt Enable: Writing a "1" to this bit enables Alarm Indication Signal detection interrupt generation, writing a "0" masks it. Receive Loss of Signal Interrupt Enable: Writing a "1" to this bit enables Loss of Receive Signal interrupt generation, writing a "0" masks it. QRSS Pattern Detection Interrupt Enable: Writing a "1" to this bit enables QRSS pattern detection interrupt generation, writing a "0" masks it. RO R/W R/W 0 0 0 FUNCTION REGISTER TYPE RESET VALUE D4 LCVIE_n R/W 0 D3 NLCDIE_n R/W 0 D2 AISDIE_n R/W 0 D1 RLOSIE_n R/W 0 D0 QRPDIE_n R/W 0 53 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION REGISTER ADDRESS 0000101 0010101 0100101 0110101 BIT # D7 D6 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved DMO_n Driver Monitor Output: This bit is set to a "1" to indicate transmit driver failure is detected. The value of this bit is based on the current status of DMO for the corresponding channel. If the DMOIE bit is enabled, any transition on this bit will generate an Interrupt. FiFO Limit Status: This bit is set to a "1" to indicate that the jitter attenuator read/write FIFO pointers are within +/- 3 bits. If the FLSIE bit is enabled, any transition on this bit will generate an Interrupt. Line Code Violation: This bit is set to a "1" to indicate that the receiver of channel n is currently detecting a Line Code Violation or an excessive number of zeros in the B8ZS or HDB3 modes. If the LCVIE bit is enabled, any transition on this bit will generate an Interrupt. RO RO 0 0 FUNCTION REGISTER TYPE RESET VALUE D5 FLS_n RO 0 D4 LCV_n RO 0 54 PRELIMINARY D3 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION NLCD_n Network Loop-Code Detection: This bit operates differently in the Manual or the Automatic Network Loop-Code detection modes. In the Manual Loop-Code detection mode, (NLCDE1 = "0" and NLCDE0 = "1" or NLCDE1 = "1" and NLCDE0 = "0") this bit gets set to "1" as soon as the Loop-Up ("00001") or LoopDown ("001") code is detected in the receive data for longer than 5 seconds. The NLCD bit stays in the "1" state for as long as the chip detects the presence of the Loop-code in the receive data and it is reset to "0" as soon as it stops receiving it. In this mode, if the NLCD interrupt is enabled, the chip will initiate an interrupt on every transition of the NLCD. When the Automatic Loop-code detection mode, (NLCDE1 = "1" and NLCDE0 ="1") is initiated, the state of the NLCD interface bit is reset to "0" and the chip is programmed to monitor the receive input data for the Loop-Up code. This bit is set to a "1" to indicate that the Network Loop Code is detected for more than 5 seconds. Simultaneously the Remote Loop-Back condition is automatically activated and the chip is programmed to monitor the receive data for the Network Loop Down code. The NLCD bit stays in the "1" state for as long as the Remote Loop-Back condition is in effect even if the chip stops receiving the Loop-Up code. Remote Loop-Back is removed if the chip detects the "001" pattern for longer than 5 seconds in the receive data.Detecting the "001" pattern also results in resetting the NLCD interface bit and initiating an interrupt provided the NLCD interrupt enable bit is active. When programmed in Automatic detection mode, the NLCD interface bit stays "High" for the entire time the Remote Loop-Back is active and initiate an interrupt anytime the status of the NLCD bit changes. In this mode, the Host can monitor the state of the NLCD bit to determine if the Remote LoopBack is activated. Alarm Indication Signal Detect: This bit is set to a "1" to indicate All Ones Signal is detected by the receiver. The value of this bit is based on the current status of Alarm Indication Signal detector of channel n. If the AISDIE bit is enabled, any transition on this bit will generate an Interrupt. Receive Loss of Signal: This bit is set to a "1" to indicate that the receive input signal is lost. The value of this bit is based on the current status of the receive input signal of channel n. If the RLOSIE bit is enabled, any transition on this bit will generate an Interrupt. Quasi-random Pattern Detection: This bit is set to a "1" to indicate the receiver is currently in synchronization with QRSS pattern. The value of this bit is based on the current status of Quasi-random pattern detector of channel n. If the QRPDIE bit is enabled, any transition on this bit will generate an Interrupt. RO 0 D2 AISD_n RO 0 D1 RLOS_n RO 0 D0 QRPD_n RO 0 55 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION REGISTER ADDRESS 0000110 0010110 0100110 0110110 BIT # D7 D6 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved DMOIS_n Driver Monitor Output Interrupt Status: This bit is set to a "1" every time the DMO status has changed since last read. RO RUR 0 0 FUNCTION REGISTER TYPE RESET VALUE NOTE: This bit is reset upon read. D5 FLSIS_n FIFO Limit Interrupt Status: This bit is set to a "1" every time when FIFO Limit (Read/Write pointer with +/- 3 bits apart) status has changed since last read. RUR 0 NOTE: This bit is reset upon read. D4 LCVIS_n Line Code Violation Interrupt Status: This bit is set to a "1" every time when LCV status has changed since last read. RUR 0 NOTE: This bit is reset upon read. D3 NLCDIS_n Network Loop-Code Detection Interrupt Status: This bit is set to a "1" every time when NLCD status has changed since last read. RUR 0 NOTE: This bit is reset upon read. D2 AISDIS_n AIS Detection Interrupt Status: This bit is set to a "1" every time when AISD status has changed since last read. RUR 0 NOTE: This bit is reset upon read. D1 RLOSIS_n Receive Loss of Signal Interrupt Status: This bit is set to a "1" every time RLOS status has changed since last read. RUR 0 NOTE: This bit is reset upon read. D0 QRPDIS_n Quasi-Random Pattern Detection Interrupt Status: This bit is set to a "1" every time when QRPD status has changed since last read. RUR 0 NOTE: This bit is reset upon read. 56 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION REGISTER ADDRESS 0000111 0010111 0100111 0110111 BIT # D7 D6 D5 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved Reserved CLOS5_n Cable Loss bit 5: CLOS[5:0]_n are the six bit receive selective equalizer setting which is also a binary word that represents the cable attenuation indication within 1dB. CLOS5_n is the most significant bit (MSB) and CLOS0_n is the least significant bit (LSB). Cable Loss bit 4: See description of D5 for function of this bit. Cable Loss bit 3: See description of D5 for function of this bit. Cable Loss bit 2: See description of D5 for function of this bit. Cable Loss bit 1: See description of D5 for function of this bit. Cable Loss bit 0: See description of D5 for function of this bit. RO RO RO 0 0 0 FUNCTION REGISTER TYPE RESET VALUE D4 D3 D2 D1 D0 CLOS4_n CLOS3_n CLOS2_n CLOS1_n CLOS0_n RO RO RO RO RO 0 0 0 0 0 57 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION REGISTER ADDRESS 0001000 0011000 0101000 0111000 BIT # D7 D6-D0 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved B6S1_n B0S1_n Arbitrary Transmit Pulse Shape, Segment 1:The shape of each channel's transmitted pulse can be made independently user programmable by selecting "Arbitrary Pulse" mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the first time segment. B6S1_nB0S1_n is in signed magnitude format with B6S1_n as the sign bit and B0S1_n as the least significant bit (LSB). R/W R/W 0 0 FUNCTION REGISTER TYPE RESET VALUE TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION REGISTER ADDRESS 0001001 0011001 0101001 0111001 BIT # D7 D6-D0 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved B6S2_n B0S2_n Arbitrary Transmit Pulse Shape, Segment 2 The shape of each channel's transmitted pulse can be made independently user programmable by selecting "Arbitrary Pulse" mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the second time segment. B6S2_nB0S2_n is in signed magnitude format with B6S2_n as the sign bit and B0S2_n as the least significant bit (LSB). R/W R/W 0 0 FUNCTION REGISTER TYPE RESET VALUE 58 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 29: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION REGISTER ADDRESS 0001010 0011010 0101010 0111010 BIT # D7 D6-D0 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved B6S3_n B0S3_n Arbitrary Transmit Pulse Shape, Segment 3 The shape of each channel's transmitted pulse can be made independently user programmable by selecting "Arbitrary Pulse" mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the third time segment. B6S3_nB0S3_n is in signed magnitude format with B6S3_n as the sign bit and B0S3_n as the least significant bit (LSB). R/W R/W 0 0 FUNCTION REGISTER TYPE RESET VALUE TABLE 30: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION REGISTER ADDRESS 0001011 0011011 0101011 0111011 BIT # D7 D6-D0 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved B6S4_n B0S4_n Arbitrary Transmit Pulse Shape, Segment 4 The shape of each channel's transmitted pulse can be made independently user programmable by selecting "Arbitrary Pulse" mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the fourth time segment. B6S4_nB0S4_n is in signed magnitude format with B6S4_n as the sign bit and B0S4_n as the least significant bit (LSB). R/W R/W 0 0 FUNCTION REGISTER TYPE RESET VALUE 59 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION REGISTER ADDRESS 0001100 0011100 0101100 0111100 BIT # D7 D6-D0 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved B6S5_n B0S5_n Arbitrary Transmit Pulse Shape, Segment 5 The shape of each channel's transmitted pulse can be made independently user programmable by selecting "Arbitrary Pulse" mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the fifth time segment. B6S5_nB0S5_n is in signed magnitude format with B6S5_n as the sign bit and B0S5_n as the least significant bit (LSB). R/W R/W 0 0 FUNCTION REGISTER TYPE RESET VALUE TABLE 32: MICROPROCESSOR REGISTER #13, BIT DESCRIPTION REGISTER ADDRESS 0001101 0011101 0101101 0111101 BIT # D7 D6-D0 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved B6S6_n B0S6_n Arbitrary Transmit Pulse Shape, Segment 6 The shape of each channel's transmitted pulse can be made independently user programmable by selecting "Arbitrary Pulse" mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the sixth time segment. B6S6_nB0S6_n is in signed magnitude format with B6S6_n as the sign bit and B0S6_n as the least significant bit (LSB). R/W R/W 0 0 FUNCTION REGISTER TYPE RESET VALUE 60 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 33: MICROPROCESSOR REGISTER #14, BIT DESCRIPTION REGISTER ADDRESS 0001110 0011110 0101110 0111110 BIT # D7 D6-D0 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved B6S7_n B0S7_n Arbitrary Transmit Pulse Shape, Segment 7 The shape of each channel's transmitted pulse can be made independently user programmable by selecting "Arbitrary Pulse" mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the seventh time segment. B6S7_n-B0S7_n is in signed magnitude format with B6S7_n as the sign bit and B0S7_n as the least significant bit (LSB). R/W R/W 0 0 FUNCTION REGISTER TYPE RESET VALUE TABLE 34: MICROPROCESSOR REGISTER #15, BIT DESCRIPTION REGISTER ADDRESS 0001111 0011111 0101111 0111111 BIT # D7 D6-D0 CHANNEL_n CHANNEL_0 CHANNEL_1 CHANNEL_2 CHANNEL_3 NAME Reserved B6S8_n B0S8_n Arbitrary Transmit Pulse Shape, Segment 8 The shape of each channel's transmitted pulse can be made independently user programmable by selecting "Arbitrary Pulse" mode in Table 5. The arbitrary pulse is divided into eight time segments whose combined duration is equal to one period of MCLK. This 7 bit number represents the amplitude of the nth channel's arbitrary pulse during the eighth time segment. B6S8_nB0S8_n is in signed magnitude format with B6S8_n as the sign bit and B0S8_n as the least significant bit (LSB). R/W R/W 0 0 FUNCTION REGISTER TYPE RESET VALUE 61 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 35: MICROPROCESSOR REGISTER #64, BIT DESCRIPTION REGISTER ADDRESS 1000000 BIT # D7 SR/DR Single-rail/Dual-rail Select: Writing a "1" to this bit configures all 8 channels in the XRT83L34 to operate in the Single-rail mode. Writing a "0" configures the XRT83L34 to operate in Dual-rail mode. Automatic Transmit All Ones Upon RLOS: Writing a "1" to this bit enables the automatic transmission of All "Ones" data to the line for the channel that detects an RLOS condition. Writing a "0" disables this feature. Receive Clock Edge: Writing a "1" to this bit selects receive output data of all channels to be updated on the negative edge of RCLK. Wring a "0" selects data to be updated on the positive edge of RCLK. Transmit Clock Edge: Writing a "0" to this bit selects transmit data at TPOS_n/TDATA_n and TNEG_n/CODES_n of all channels to be sampled on the falling edge of TCLK_n. Writing a "1" selects the rising edge of the TCLK_n for sampling. DATA Polarity: Writing a "0" to this bit selects transmit input and receive output data of all channels to be active "High". Writing a "1" selects an active "Low" state. R/W 0 REGISTER TYPE RESET VALUE NAME FUNCTION D6 ATAOS R/W 0 D5 RCLKE R/W 0 D4 TCLKE R/W 0 D3 DATAP R/W 0 D2 D1 Reserved GIE Global Interrupt Enable: Writing a "1" to this bit globally enables interrupt generation for all channels. Writing a "0" disables interrupt generation. Software Reset P Registers: Writing a "1" to this bit longer than 10s initiates a device reset through the microprocessor interface. All internal circuits are placed in the reset state with this bit set to a "1" except the microprocessor register bits. R/W 0 0 D0 SRESET R/W 0 62 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 CLOCK SELECT REGISTER The input clock source is used to generate all the necessary clock references internally to the LIU. The microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits and the Master Clock Rate in register 0x41h. Therefore, if the clock selection bits or the MCLRATE bit are being programmed, the frequency of the PLL output will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within the same register while selecting the input/output clock frequency. For best results, when bits D[6:3] are being changed, the other bits D[7] and D[2:0] as shown in Figure 25. should retain their previous values. FIGURE 25. REGISTER 0X81H SUB REGISTERS D7 D6 D5 D4 D3 D2 D1 D0 E1arben Clock Selection Bits ExLOS, ICT Programming Examples: Example 1: Changing bits D[6:3] If bits D[6:3] are the only values within the register that will change in a WRITE process, the microprocessor only needs to initiate ONE write operation. Example 2: Changing bits D[7] and D[2:0] If bits D[7] and D[2:0] are the only values within the register that will change in a WRITE process, the microprocessor only needs to initiate ONE write operation. Example 3: Changing bits within D[6:3] and the other bits In this scenario, one must initiate TWO write operations such that bits D[6:3] and the other bits do not change within ONE write cycle. It is recommended that bits D[6:0] and the other bits be treated as two independent sub-registers. One can either change the clock selection bits and then change bits D[7] and D[2:0] on the SECOND write, or vice-versa. No order or sequence is necessary. 63 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 36: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION REGISTER ADDRESS 1000001 BIT # D7 E1arben E1 Arbitrary Pulse Enable This bit is used to enable the Arbitrary Pulse Generators for shaping the transmit pulse shape when E1 mode is selected. If this bit is set to "1", all 8 channels will be configured for the Arbitrary Mode. However, each channel is individually controlled by programming the channel registers 0xn8 through 0xnF, where n is the number of the channel. "0" = Disabled (Normal E1 Pulse Shape ITU G.703) "1" = Arbitrary Pulse Enabled Clock Select Inputs for Master Clock Synthesizer bit 2: In Host mode, CLKSEL[2:0] are input signals to a programmable frequency synthesizer that can be used to generate a master clock from an external accurate clock source according to the following table; M CLKE1 kHz 2048 2048 2048 1544 1544 2048 8 8 16 16 56 56 64 64 128 128 256 256 M CLKT1 kHz 2048 2048 1544 1544 1544 1544 X X X X X X X X X X X X CLKSEL2 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CLKSEL1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CLKSEL0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 M CLKRATE 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLKOUT/ kHz 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 2048 1544 NAME FUNCTION REGISTER TYPE R/W RESET VALUE 0 D6 CLKSEL2 R/W 0 In Hardware mode, the state of these signals are ignored and the master frequency PLL is controlled by the corresponding Hardware pins. D5 CLKSEL1 Clock Select inputs for Master Clock Synthesizer bit 1: See description of bit D6 for function of this bit. Clock Select inputs for Master Clock Synthesizer bit 0: See description of bit D6 for function of this bit. R/W 0 D4 CLKSEL0 R/W 0 64 PRELIMINARY D3 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 36: MICROPROCESSOR REGISTER #65, BIT DESCRIPTION MCLKRATE Master clock Rate Select: The state of this bit programs the Master Clock Synthesizer to generate the T1/J1 or E1 clock. The Master Clock Synthesizer will generate the E1 clock when MCLKRATE = "0", and the T1/J1 clock when MCLKRATE = "1". Receive Output Mute: Writing a "1" to this bit, mutes receive outputs at RPOS/RDATA and RNEG/LCV pins to a "0" state for any channel that detects an RLOS condition. R/W 0 D2 RXMUTE R/W 0 NOTE: RCLK is not muted. D1 EXLOS Extended LOS: Writing a "1" to this bit extends the number of zeros at the receive input of each channel before RLOS is declared to 4096 bits. Writing a "0" reverts to the normal mode (175+75 bits for T1 and 32 bits for E1). In-Circuit-Testing: Writing a "1" to this bit configures all the output pins of the chip in high impedance mode for In-CircuitTesting. Setting the ICT bit to "1" is equivalent to connecting the Hardware ICT pin 88 to ground. R/W 0 D0 ICT R/W 0 TABLE 37: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION REGISTER ADDRESS 1000010 BIT # D7 GAUGE1 Wire Gauge Selector Bit 1: This bit together with bit D6 are used to select wire gauge size as shown in the table below. R/W 0 REGISTER TYPE RESET VALUE NAME FUNCTION GAUGE1 0 0 1 1 D6 GAUGE0 GAUGE0 0 1 0 1 Wire Size 22 and 24 Gauge 22 Gauge 24 Gauge 26 Gauge R/W 0 Wire Gauge Selector Bit 0: See bit D7. Transmit On Control: In Host mode, setting this bit to "1" transfers the control of the Transmit On/Off function to the TXON_n Hardware control pins. D5 TXONCNTL R/W 0 NOTE: This provides a faster On/Off capability for redundancy application. D4 TERCNTL Termination Control. In Host mode, setting this bit to "1" transfers the control of the RXTSEL to the RXTSEL Hardware control pin. R/W 0 NOTE: This provides a faster On/Off capability for redundancy application. 65 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY R/W 0 TABLE 37: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION D3 SL_1 Slicer Level Control bit 1: This bit and bit D2 control the slicing level for the slicer per the following table. SL_1 0 0 1 1 SL_0 0 1 0 1 Normal Decrease by 5% from Normal Increase by 5% from Normal Normal Slicer Mode D2 D1 SL_0 EQG_1 Slicer Level Control bit 0: See description bit D3. Equalizer Gain Control bit 1: This bit together with bit D0 control the gain of the equalizer as shown in the table below. EQG_1 0 0 1 1 EQG_0 0 1 0 1 Equalizer Gain Normal Reduce Gain by 1 dB Reduce Gain by 3 dB Normal R/W R/W 0 0 D0 EQG_0 Equalizer Gain Control bit 0: See description of bit D1 R/W 0 66 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 ELECTRICAL CHARACTERISTICS TABLE 38: ABSOLUTE MAXIMUM RATINGS Storage Temperature...................-65C to + 150C Operating Temperature.............-40C to + 85C Supply Voltage..........................-0.5V to + 3.8V VIn.................................................-0.5V to + 5.5V TABLE 39: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS VDD=3.3V5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage @ IOH = 2.0mA Output Low Voltage @IOL = 2mA. Input Leakage Current (except Input pins with Pull-up or Pull- down resistor). Input Capacitance Output Load Capacitance SYMBOL VDD VIH VIL V OH VOL IL CI CL MIN. 3.13 2.0 -0.5 2.4 TYP. 3.3 5.0 MAX. 3.46 5.0 0.8 0.4 10 25 UNITS V V V V V A pF pF TABLE 40: XRT83L34 POWER CONSUMPTION VDD=3.3V5%, TA=25C, UNLESS OTHERWISE SPECIFIED MODE E1 SUPPLY VOLTAGE 3.3V IMPEDANCE 75 TERMINATION TRANSFORMER RATIO TYP. RECEIVER TRANSMITTER 1:1 1:2.45 510 740 500 625 455 480 420 440 720 1050 mW mW mW mW mW mW mW mW mW mW MAX. UNIT RESISTOR 6.2 TEST CONDITIONS 50% "1's" 100% "1's" 50% "1's" 100% "1's" 50% "1's" 100% "1's" 50% "1's" 100% "1's" 50% "1's" 100% "1's" E1 3.3V 75 9.1 1:1 1:2 E1 3.3V 120 6.2 1:1 1:2.45 E1 3.3V 120 9.1 1:1 1:2 T1 3.3V 100 3 1:1 1:2.45 67 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 40: XRT83L34 POWER CONSUMPTION VDD=3.3V5%, TA=25C, UNLESS OTHERWISE SPECIFIED MODE T1 SUPPLY VOLTAGE 3.3V IMPEDANCE 100 TERMINATION TRANSFORMER RATIO TYP. RECEIVER TRANSMITTER 1:1 1:2 820 1050 230 mW mW mW MAX. UNIT RESISTOR 3 TEST CONDITIONS 50% "1's" 100% "1's" All transmitters off --- 3.3V --- --- --- --- TABLE 41: E1 RECEIVER ELECTRICAL CHARACTERISTICS VDD=3.3V5%, TA= -40 TO 85C, UNLESS OTHERWISE SPECIFIED PARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS De-asserted Receiver Sensitivity (Short Haul with cable loss) 15 12.5 11 MIN. TYP. MAX. UNIT TEST CONDITIONS Cable attenuation @1024kHz 32 20 dB % ones dB With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75 application. With -18dB interference signal added. With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75 application. With -18dB interference signal added. ITU-G.775, ETSI 300 233 Receiver Sensitivity (Long Haul with cable loss) 0 43 dB Input Impedance Input Jitter Tolerance: 1 Hz 10kHz-100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency (-3dB curve) (JABW=0) (JABW=1) Return Loss: 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 13 k 37 0.2 UIpp UIpp ITU G.823 - 36 -0.5 kHz dB ITU G.736 - 10 1.5 - Hz Hz ITU G.736 14 20 16 - - dB dB dB ITU-G.703 68 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 42: T1 RECEIVER ELECTRICAL CHARACTERISTICS VDD=3.3V5%, TA=-40 TO 85C, UNLESS OTHERWISE SPECIFIED PARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS Clear Receiver Sensitivity (Short Haul with cable loss) Receiver Sensitivity (Long Haul with cable loss) Normal Extended Input Impedance Jitter Tolerance: 1Hz 10kHz - 100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency (-3dB curve) Return Loss: 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 160 175 190 MIN. TYP. MAX. UNIT TEST CONDITIONS 15 12.5 12 20 - - dB % ones dB Cable attenuation @772kHz ITU-G.775, ETSI 300 233 With nominal pulse amplitude of 3.0V for 100 termination 0 0 13 36 45 dB dB k With nominal pulse amplitude of 3.0V for 100 termination 138 0.4 - - UIpp AT&T Pub 62411 - 9.8 0.1 KHz dB -Hz TR-TSY-000499 6 AT&T Pub 62411 - 20 25 25 - dB dB dB TABLE 43: E1 TRANSMIT RETURN LOSS REQUIREMENT RETURN LOSS FREQUENCY G.703/CH-PTT 51-102kHz 102-2048kHz 2048-3072kHz 8dB 14dB 10dB ETS 300166 6dB 8dB 8dB 69 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY TABLE 44: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS VDD=3.3V5%, TA=-40 TO 85C, UNLESS OTHERWISE SPECIFIED PARAMETER AMI Output Pulse Amplitude: 75 Application 120 Application Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio Jitter Added by the Transmitter Output Output Return Loss: 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz 2.13 2.70 224 0.95 0.95 2.37 3.00 244 0.025 2.60 3.30 264 1.05 1.05 0.05 V V ns UIpp ITU-G.703 ITU-G.703 Broad Band with jitter free TCLK applied to the input. MIN. TYP. MAX. UNIT TEST CONDITIONS Transformer with 1:2 ratio and 9.1 resistor in series with each end of primary. 8 14 10 - - dB dB dB ETSI 300 166, CHPTT TABLE 45: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS VDD=3.3V5%, TA=-40 TO 85C, UNLESS OTHERWISE SPECIFIED PARAMETER AMI Output Pulse Amplitude: Output Pulse Width Output Pulse Width Imbalance Output Pulse Amplitude Imbalance Jitter Added by the Transmitter Output Output Return Loss: 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz MIN. 2.4 338 TYP. 3.0 350 0.025 MAX. 3.60 362 20 +200 0.05 UNIT V ns mV UIpp TEST CONDITIONS Use transformer with 1:2.45 ratio and measured at DSX-1 ANSI T1.102 ANSI T1.102 ANSI T1.102 Broad Band with jitter free TCLK applied to the input. - 15 15 15 - dB dB dB 70 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 FIGURE 26. ITU G.703 PULSE TEMPLATE 269 ns (244 + 25) 20% 10% V = 100% 10% 20% 194 ns (244 - 50) Nominal pulse 50% 244 ns 10% 488 ns (244 + 244) Note - V corresponds to the nominal peak value. TABLE 46: TRANSMIT PULSE MASK SPECIFICATION Test Load Impedance Nominal Peak Voltage of a Mark Peak voltage of a Space (no Mark) Nominal Pulse width Ratio of Positive and Negative Pulses Imbalance 75 Resistive (Coax) 2.37V 0 + 0.237V 244ns 0.95 to 1.05 120 Resistive (twisted Pair) 3.0V 0 + 0.3V 244ns 0.95 to 1.05 20% 71 10% 0% 10% 10% 219 ns (244 - 25) XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY FIGURE 27. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE) TABLE 47: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS MINIMUM CURVE TIME (UI) -0.77 -0.23 -0.23 -0.15 0.0 0.15 0.23 0.23 0.46 0.66 0.93 1.16 NORMALIZED AMPLITUDE -.05V -.05V 0.5V 0.95V 0.95V 0.9V 0.5V -0.45V -0.45V -0.2V -0.05V -0.05V TIME (UI) -0.77 -0.39 -0.27 -0.27 -0.12 0.0 0.27 0.35 0.93 1.16 MAXIMUM CURVE NORMALIZED AMPLITUDE .05V .05V .8V 1.15V 1.15V 1.05V 1.05V -0.07V 0.05V 0.05V 72 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 48: AC ELECTRICAL CHARACTERISTICS VDD=3.3V5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER E1 MCLK Clock Frequency T1 MCLK Clock Frequency MCLK Clock Duty Cycle MCLK Clock Tolerance TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TCLK Rise Time(10%/90%) TCLK Fall Time(90%/10%) RCLK Duty Cycle Receive Data Setup Time Receive Data Hold Time RCLK to Data Delay RCLK Rise Time(10% to 90%) with 25pF Loading. RCLK Fall Time(90% to 10%) with 25pF Loading. TCDU TSU THO TCLKR TCLKF RCDU RSU RHO RDY RCLKR RCLKF SYMBOL MIN. 40 30 50 30 45 150 150 TYP. 2.048 1.544 50 50 50 60 70 40 40 55 40 40 40 MAX. UNITS MHz MHz % ppm % ns ns ns ns % ns ns ns ns ns FIGURE 28. TRANSMIT CLOCK AND INPUT DATA TIMING TCLKR TCLKF TCLK TPOS/TDATA or TNEG TSU THO 73 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY FIGURE 29. RECEIVE CLOCK AND OUTPUT DATA TIMING RDY RCLKR RCLKF RCLK RPOS or RNEG RHO MICROPROCESSOR INTERFACE I/O TIMING INTEL INTERFACE TIMING - ASYNCHRONOUS The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD), Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum external glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency, and with the timings of x86 or i960 family or microprocessors. The interface timing shown in Figure 30 and Figure 32 is described in Table 49. FIGURE 30. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING R E A D O PE R A T IO N A LE _A S W R IT E O P ER A T IO N t0 A D D R [6 :0 ] t5 CS Va lid A ddress t0 V alid Ad dre ss t5 D A T A [7 :0] t1 R D _D S V alid D ata for R ead ba ck D ata A vaila ble to W rite In to th e LIU t3 W R _R /W t2 t4 R D Y_ D T AC K 74 PRELIMINARY XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 TABLE 49: ASYNCHRONOUS MODE 1 - INTEL 8051 AND 80188 INTERFACE TIMING SYMBOL t0 t1 t2 NA t3 t4 NA t5 PARAMETER Valid Address to CS Falling Edge CS Falling Edge to RD Assert RD Assert to RDY Assert RD Pulse Width (t2) CS Falling Edge to WR Assert WR Assert to RDY Assert WR Pulse Width (t2) CS Falling Edge to AS Falling Edge MIN 0 65 50 65 50 0 MAX 50 50 UNITS ns ns ns ns ns ns ns ns Reset pulse width - both Motorola and Intel Operations (see Figure 32) t9 Reset pulse width 30 75 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY MOTOROLA ASYCHRONOUS INTERFACE TIMING The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS), Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible with the timing of a Motorola 68000 microprocessor family with up to 16.67 MHz clock frequency. The interface timing is shown in Figure 31 and Figure 32. The I/O specifications are shown in Table 50. FIGURE 31. MOTOROLA 68K ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING R E A D O P E R A T IO N A LE _ A S t0 A D D R [6 :0] t3 CS V a lid A d dress t0 V a lid A d dress W R IT E O P E R A TIO N t3 D A T A [7:0 ] t1 R D _D S V alid D ata for Re adbac k t1 Data A v ailable to W rite Into the LIU W R_ R/W t2 t2 R DY _D TA C K TABLE 50: ASYNCHRONOUS - MOTOROLA 68K - INTERFACE TIMING SPECIFICATION SYMBOL t0 t1 t2 NA t3 PARAMETER Valid Address to CS Falling Edge CS Falling Edge to DS Assert DS Assert to DTACK Assert DS Pulse Width (t2) CS Falling Edge to AS Falling Edge MIN 0 65 50 0 MAX 50 UNITS ns ns ns ns ns Reset pulse width - both Motorola and Intel Operations (see Figure 32) t9 Reset pulse width 30 FIGURE 32. MICROPROCESSOR INTERFACE TIMING - RESET PULSE WIDTH t9 Reset 76 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR PRELIMINARY ORDERING INFORMATION PART NUMBER XRT83L34IV PACKAGE 128 Pin TQFP(14x20x1.4mm) REV. P1.3.4 OPERATING TEMPERATURE RANGE -40C to +85C PACKAGE DIMENSIONS - 14X20 MM, 128 PIN PACKAGE D D1 102 65 103 64 E1 E 128 39 A2 1 e B 38 A C A1 L Note: The control dimensions are the millimeter column INCHES SYMBOL A A1 A2 B C D D1 E E1 e L MILLIMETERS MAX MIN 1.40 0.05 1.35 0.17 0.09 21.80 19.90 15.80 13.90 MAX 1.60 0.15 1.45 0.27 0.20 22.20 20.10 16.20 14.10 MIN 0.0551 0.0020 0.0531 0.0067 0.0035 0.8583 0.7835 0.6220 0.5472 0.0630 0.0059 0.0571 0.0106 0.0079 0.8740 0.7913 0.6378 0.5551 0.0197 BSC 0.0177 0o 0.0295 7o 0.50 BSC 0.45 0o 0.75 7o 77 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY REVISIONS REVISION A1.0.1 thru A1.0.7 P1.1.0 P1.2.0 Advanced Versions DESCRIPTION Preliminary release version Added GHCI_n, SL_1, SL_0, EQG_1 and EQG_0 to Control Global Register 131. Separated Microprocessor description table by register number. Moved absolute maximum and Dc electrical characteristics before AC electrical characteristics. Replaced TBD's in electrical ables. Reformated table of contents. Added GAUGE1 and GAUGE0 to Control Global Register 131. Corrected control register binary bits. Renamed FIFO pin to GAUGE, edited definition and edited defintion of JASEL[1:0] to reflect the FIFO size is selected by the jitter attenuator select. Redefined bits D3, D2 and D0 of register 1, in combination these bits set the jitter attenuator path and FIFO size. Corrected typos in figures 6 and 8. Added Jitter attenuator tables in microprocessor register tables. Modified microprocessor descrptions, timing diagrams and electrical characteristics. Replaced GCHIE with Reserved in Tables 18, 23, 24,25. In the pin list description for INT, replace IMASK bit to a "1" with GIE bit to a "0". New description for bits D6 - D0 in Tables 27 - 34 Microprocessor Registers. Revised Microprocessor interface timing diagrams and data. Corrected microprocessor timing information and edited Redundancy section. Edited section on RLOS for more detailed explanation. Changed definition of TXON_n pin. RXON_n bit included in register tables. Rx transformer ratio changed from 2:1 to 1:1. Description of Arbitrary Pulse and Gap Clock support added. Minor edits to block diagram, changed issue date to January, corrected register 67 in table 18, corrected table 37. Swapped the function of PTS1 and PTS2. Replaced Processor timing diagrams and timing information, (Figures 29 and 30 -- Tables 49 and 50). Updated the Power Consumption numbers. Added the New E1 Arbitrary Pulse Feature. Added descriptions to the global registers. P1.2.1 P1.2.2 P1.2.3 P1.2.4 P1.2.5 P1.2.6 P1.2.7 P1.2.8 P1.2.9 P1.3.0 P1.3.1 P1.3.2 P1.3.3 P1.3.4 78 XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. P1.3.4 PRELIMINARY NOTES: NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2004 EXAR Corporation Datasheet February 2004. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 79 |
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